I am a passionate and self-motivated circuit designer with close to 12 years of experience in the back end design of microprocessors, My expertise lies in the areas of digital design and low power design. All along, my focus has been on both execution and innovation. I am a strong proponent of the fact that our designs are as good as we execute them. I strive to find the smallest of opportunities for design improvements and innovations. I have tried to showcase my work at multiple internal and external conferences including DAC, SNUG, CDN Live and Mentor U2U.I have primarily worked on custom designs like the Real Time Clock, Power Supply Monitor, True Random Number Generator and designs for clock distribution. I have also owned a design which was done through the Physical Design (PD) approach. As the owner of custom designs, my key tasks have been: • Formal Equivalence Verification (RTL – Netlist match)• Generation of schematics (gate level design) by understanding the RTL • Analysis of layout’s (Block placement, routing of signals)• Performance Validation – Static Timing Analysis, Noise and Reliability Verification• Electrical analysis - EMIR sign-off • Taking the blocks through to closure during execution for the milestonesI also have a keen interest in design methodologies and CAD methodologies and tools. Over the years, I have played a key role in driving the design and CAD methodology for the circuits team. A little more about me ... I am an optimist by nature and a fun loving person. I love to share my ideas and thoughts with my fellow colleagues and believe I am a good team player. I truly believe in the saying "Together, we can achieve more".