Krupen Patel

Krupen Patel Email and Phone Number

System Validation Engineer at Intel Corporation @ Intel Corporation
Folsom, CA, US
Krupen Patel's Location
Folsom, California, United States, United States
Krupen Patel's Contact Details

Krupen Patel personal email

n/a
About Krupen Patel

-Master of Science in computer Engineering.-Field experience for working in industry for implementing knowledge of instrumentation and control.-Strong experience of being a Technical Writer Student Assistant, which adds skill of Engineering Ethics to my profile.-Hardworker, Team player. ----------------------------------------------Technical Skills :----------------------------------------------------------------Languages: C,C++, PythonOperating environment: Windows, Linux-Writing scripts for automation in python .-Knowledge of use of various buses according to requirement of architecture.-Post Silicon validation.-Probe and bench level wafer testing for temperature and voltage.----------------------------------------------Interpersonal Skills :-----------------------------------------------------------------Working in environment of team-Dedication towards work- Communication and writing skills -Taking initiatives

Krupen Patel's Current Company Details
Intel Corporation

Intel Corporation

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System Validation Engineer at Intel Corporation
Folsom, CA, US
Website:
intel.com
Employees:
114813
Krupen Patel Work Experience Details
  • Intel Corporation
    Intel Corporation
    Folsom, Ca, Us
  • Intel Corporation
    System Validation Engineer
    Intel Corporation Dec 2019 - Present
    Santa Clara, California, Us
    Life Cycle Management:• Develop a test plan for post-silicon validation to ensure it meets all performance, reliability, and safety requirements for CPU products.• Responsible for CMV (Circuit Marginality Validation) validation planning across the product roadmap with voltage and Temperature (PVT) to reduce DPM to help the HVM team.Testing / debug / Strategic Problem Solving:• Planning and executing system validation plans to identify marginality failures of products.• Creating automated test plans, developing content, and debugging any issues for HSIO like PCIE gen 5, PCIE gen 4 , USB 32 , TCSS etc• Developed strategy and methodology for new binning features which were implemented on the POR products with a methodology to help the products' stakeholders.• Providing system-side critical debug expertise and support for high-fallout DPM excursions and customer returns products.• Developed automation scripts for the auto system (auto robot), which runs the SOC in volume and gives the results. Characterization flow:• Developed tests that include Voltage margin and Temperature flows with the IP test content, which will help the DPM and HVM team kill those materials for better Yield and DPM. • Develop Shmoo and search flow with PVT to help the DPM team and external customers to debug the IP.Cross-functional communication and collaboration:• Collaborating with different functional teams (Class team, IP validation team, BIOS (IFWI) team, Windows team, HVM, DPM teams) across the organization to achieve a smooth and efficient validation process through the product.• Developed and delivered comprehensive training for team members and cross-functional teams.Achievements:• Awards for reducing the DPM defects for the competing products.• Awards for new-gen IP debugging and helping external customers.
  • Attala Systems
    Engineering Intern
    Attala Systems Mar 2017 - Aug 2017
    Attala system Worked on high-performance compostable storage infrastructure, based on an Intel FPGA-based scale-out fabric. Which is mainly used for data storage interacting with cloudworked on integrating and manage data storage on the system.Modified Fio-tools for performance check of NVME drives and improved speed of the process to check
  • Gofind.Ai
    Engineering Intern
    Gofind.Ai Apr 2016 - Dec 2016
    Toronto, Ontario, Ca
  • Northwestern Polytechnic University
    Grader ( Early American History)
    Northwestern Polytechnic University Jan 2016 - Jun 2016
    Fremont, California, Us
  • Northwestern Polytechnic University
    Teaching Assistant (Unix/Linux Shell & Python Scripting)
    Northwestern Polytechnic University Jan 2016 - Jun 2016
    Fremont, California, Us

Krupen Patel Skills

Java C Html C++ Mysql Sql Javascript Python Linux Microsoft Office Unix Eclipse Matlab Php Css Html5 Xml Data Structures Oop Hadoop Object Oriented Programming Json Internet Bot Web Services Git Web Services Api Facebook Api Google Api Amazon Web Services Heroku Restful Webservices Django Cascading Style Sheets

Krupen Patel Education Details

  • California State University, Fullerton
    California State University, Fullerton
    Computer Engineering
  • San Francisco Bay University
    San Francisco Bay University
    Computer Science

Frequently Asked Questions about Krupen Patel

What company does Krupen Patel work for?

Krupen Patel works for Intel Corporation

What is Krupen Patel's role at the current company?

Krupen Patel's current role is System Validation Engineer at Intel Corporation.

What is Krupen Patel's email address?

Krupen Patel's email address is kr****@****tel.com

What schools did Krupen Patel attend?

Krupen Patel attended California State University, Fullerton, San Francisco Bay University.

What skills is Krupen Patel known for?

Krupen Patel has skills like Java, C, Html, C++, Mysql, Sql, Javascript, Python, Linux, Microsoft Office, Unix, Eclipse.

Who are Krupen Patel's colleagues?

Krupen Patel's colleagues are Brien Blankenship, Prem Jetti, Binfen Zhang, David González García, John Pontier, Swaathi Sampath, Edward Kearns.

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