As a Senior Application Engineer at Cadence Design Systems, I work with leading semiconductor companies to provide them with innovative and customized solutions for physical design. I use my expertise in place and route (P&R) tools and methodologies to optimize the performance, power, and area of their chips, and to resolve any technical issues or challenges they face.I have a strong background in VLSI design, having obtained my Master of Technology from Amrita Vishwa Vidyapeetham, where I learned advanced concepts and techniques in this domain. I also have a Bachelor of Engineering in Electronics Engineering from University of Mumbai, where I developed my foundational skills and knowledge in this field. I am proficient in various P&R tools, such as Genus, Innovus, Tempus, and have a publications related to P&R techniques and algorithms.I am passionate about driving innovation and speeding up chips, and I constantly seek to learn new skills and technologies to enhance my capabilities and deliver value to my clients. I am also a team player, who enjoys collaborating with colleagues, partners, and customers to achieve shared goals and objectives. I am open to new opportunities that will challenge me and allow me to grow as a professional and as a person.