Kumar Guru Email & Phone Number

4 years of experience in all aspects of design closure (place and route, physical verification,STA) of low power,multi-million gate designs.of 28nm and lower nodes. EXPERTISE- Block Level floorplanning including macro/pin placement- Place and Route - Application of various tool options to minimize timing violations and routing overflow in the design- Clock tree synthesis - Clock Tree Synthesis and optimization of Clock path to meet the skew targets and latency constraints- Block level timing closure and noise analysis.- Physical verification - DFM activities , DRC/LVS checks and power analysis- Thorough understanding of 28/45nm technology nodes- Complete understanding of the Design flow from netlist to GDS.- Well versed with UPF flow for low power designs ToolsPhysical synthesis and PnR – Atoptech Aprisa,Synopsys IC compiler,,Design Compiler, Cadence Spectre schematic capture, Virtuoso layout editor, Modelsim,HSPICE

Listed skills include Drc, Timing Closure, Lvs, Floorplanning, and 8 others.