RISC-V Verification Engineer, specialized in Processor verification with a focus on test development for RISC-V architecture and processor verification. My expertise spans working with open-source tools and crafting custom test suites for RISC-V architecture. I'm proficient in hardware languages including RISC-V ISA, SystemVerilog, and Verilog, and skilled in various verification methodologies and tools such as Cocotb, PYVSC, and UVM. My passion lies in contributing to verification ecosystems and continuously improving verification processes.