Vice President, Software And Platform Engineering
CurrentBoard Member and Co-Chair TSC (Technical Steering Committee) of RISE (RISC-V Software Ecosystem) (http://riseproject.dev)Served as Chairman of the Platforms Horizontal Sub-Committee under RISC-V International (RVI) (https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc)✔ Head the software, platform engineering, post-silicon validation, solutions architecture, ecosystem, application engineering and support teams for Ventana's Veyron 64-bit high performance RISC-V CPU compute solution.✔ Guide product, platform, and software definition using credible insights developed by interacting with end customers, strategic partners and by following usage, market and economic trends.✔ Key Speaker at RISC-V Summit and other leading industry events.✔ Built a global multisite engineering organization at Ventana in the areas of software, performance, platforms, compilers providing hands-on leadership and direction✔ Design an architect the full RISC-V software stack including GCC and LLVM tool chains, BIOS/UEFI firmware, Linux and Android OSes, Virtualization using KVM and Xvisor, Container solutions using Kubernetes and Docker, Security solutions including Secure Boot, Middleware including OpenJDK JVM✔ Drive vision to create a unified and standardized Generative AI/ML software stack for all RISC-V platforms to avoid fragmentation in the community in joint partnership with other RISC-V partners.✔Architect and design Ventana’s Generative AI/ML accelerator software stack with efficient hardware software co-design with Tensorflow, PyTorch, ONNX using OpenAI Triton and NVIDIA CUDA platform SDKs. ✔ Architect and drive server class platforms, rack designs, accelerators for the datacenter, automotive, edge and AI/ML applications working jointly with ODMs and hardware design partners✔ Drive product evaluations at customers in the Datacenter, AI/ML, Automotive, High Performance Computing (HPC), Mobile, Networking and Storage market segments
