Research Intern
• Conducted thorough feasibility analysis on wearable and implantable devices using Human Body Communication.• Designed a EQS human body lumped circuit model, a low noise amplifier, and a rectifier for HBC RX using TSMC 65nm process.
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Kun-Chen Lee is listed as Research Intern@EPFL|BS ECE@NYCU|Analog Design Intern@NXP|HPS@Google based in Hsinchu City, Taiwan, Province of China. AeroLeads shows a matched LinkedIn profile for Kun-Chen Lee.
Kun-Chen Lee previously worked as Research Intern at Epfl and Analog Design Engineer at Nxp Semiconductors. Kun-Chen Lee holds Bachelor'S Degree, Electronics And Electrical Engineering, Cgpa: 4.25/4.3; Last 60 Gpa: 4.3/4.3; Class Ranking: 1/52 from National Yang Ming Chiao Tung University.
Kun-Chen Lee is a Research Intern@EPFL|BS ECE@NYCU|Analog Design Intern@NXP|HPS@Google.
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Geneva, Switzerland
• Conducted thorough feasibility analysis on wearable and implantable devices using Human Body Communication.• Designed a EQS human body lumped circuit model, a low noise amplifier, and a rectifier for HBC RX using TSMC 65nm process.
Hsinchu City, Taiwan, Taiwan
• Designed CMOS Voltage Reference Circuits (CVR) with 3 different topologies (2T/4T/6T) for ultra-low power IoT applications using the NXP in-house SMOS10HV technology process. • Held a 1.5-hour design review meeting to comprehensively analyze and compare the simulation results (PVT variations and Mote Carlo simulation included) between the 3 topologies and related works published on IEEE. • Constructed the testbench and simulated the Power-on Reset (POR) analog block in a… Show more • Designed CMOS Voltage Reference Circuits (CVR) with 3 different topologies (2T/4T/6T) for ultra-low power IoT applications using the NXP in-house SMOS10HV technology process. • Held a 1.5-hour design review meeting to comprehensively analyze and compare the simulation results (PVT variations and Mote Carlo simulation included) between the 3 topologies and related works published on IEEE. • Constructed the testbench and simulated the Power-on Reset (POR) analog block in a CC&SBU pin protection IC which prevents the short-to-VBUS damage in Type-C devices. • Conducting the Analog Mixed Signal (AMS) Verification of a start-up circuit. Show less
Banqiao District, New Taipei City, Taiwan
• Designed a smart clothes rail, “GOOTDLE”, to locate the clothes on the hanger using Force Sensors with Arduino UNO board and Computer Vision (CV) on Raspberry Pi. • Developed the front-end and back-end of the “Outfits Recommendation” web-based system using React and Express , connecting the application to our database created by Supabase whose data are read from the real-time monitoring of the force sensors output serials from Arduino. • Voted as the “Most Wanted Product”… Show more • Designed a smart clothes rail, “GOOTDLE”, to locate the clothes on the hanger using Force Sensors with Arduino UNO board and Computer Vision (CV) on Raspberry Pi. • Developed the front-end and back-end of the “Outfits Recommendation” web-based system using React and Express , connecting the application to our database created by Supabase whose data are read from the real-time monitoring of the force sensors output serials from Arduino. • Voted as the “Most Wanted Product” among 10 groups by up to 100 Googlers. Show less
Activities and Societies: Served as undergraduate TA for: 1. Applied Electronics, Spring 2024 (Prof. Wei-Hua Chieng) 2. Biomedical.
Transferred to National Yang Ming Chiao Tung University (NYCU) in Fall 2021
Activities and Societies: 建國中學使節團 (CKHS Student Ambassador)、游泳健身社擔任健身教學長 Top 1% out of all junior high school students in Taiwan.
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Kun-Chen Lee is listed as Research Intern@EPFL|BS ECE@NYCU|Analog Design Intern@NXP|HPS@Google.
Kun-Chen Lee is based in Hsinchu City, Taiwan, Province of China.
Kun-Chen Lee has worked for Epfl, Nxp Semiconductors, and Google.
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Kun-Chen Lee holds Bachelor'S Degree, Electronics And Electrical Engineering, Cgpa: 4.25/4.3; Last 60 Gpa: 4.3/4.3; Class Ranking: 1/52 from National Yang Ming Chiao Tung University.
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