Willy Kuo Email & Phone Number

Santa Clara, California, US

ASIC synthesis, floorplan and timing/linting/formal/CDC verification.

Subchip-level implementation from RTL to GDS in 5nm technology.

Santa Clara, California, US

• Responsible for physical synthesis RTL-to-netlist release and optimize floorplans during early chip design phase.
• Enhanced and maintained Fusion/Design Compiler Topo Synthesis flow for new design technology.
• Closely worked with architects, RTL and Physical designers for area, timing, constraints, power, and linting.
• Designed and improved floorplan for synthesis to solve timing, congestion, and interconnect.
• Conducted power reviews using PTPX from various simulation test vectors for power saving opportunities.

Santa Clara, California, US

San Jose, CA, US

• Developed CAD flow for Synopsys ICC/ICC2 P&R. Enhanced the flow for new features and tuned receipts for better quality of results. Contributed to team success by documented Wiki, supported, debug and resolved other.
• Implemented challenging timing and congestion SoC blocks from RTL to GDS using Synopsys DCG physical synthesis, ICC/ICC2 floorplanning, P&R, CTS, extraction, PT timing ECO closure, Redhawk, and ICV physical.
• Responsible for chip-level implementation using Cadence Encounter: power grid distribution; channel based repeaters place and route, timing closure, and physical verification.
• Setup infrastructure: library installation, multiple sites data mirroring, cross-views checks, QA, disk usage monitoring.

San Jose, CA, US

• Coordinated the physical design service activities with ASIC foundries and enhanced my program management and communication skills besides the following technical responsibilities.
• Implementation responsibilities: DCG physical synthesis, define timing constraints and analysis, partition/floor plan, PT-PX power calculation, logic equivalent check, clock-domain-crossing check, and post-layout.
• Tool/flow responsibilities: Enhanced and support in-house synthesis as a highly integrated and automated top-down or bottom-up flow.
• FPGA implementation using Synplify synthesis, Xilinx tools.

Implemented challenging timing and congestion SoC blocks from netlist to GDS. This startup was acquired by Cisco.

Santa Clara, California, US

Implemented challenging timing and congestion SoC blocks from netlist to GDS.

Master Of Science, Electrical Engineering

Bachelor Of Science, Physics