Willy Kuo work email
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Willy Kuo personal email
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Physical Design CAD Engineer bringing 18+ years of hands-on experiences from flow execution, development, users support to tape out. Expertise to achieve the flow automation with signoff quality.• Background in EDA software R&D with excellent programing and problem solving skills. • Extensively understand the design flow from RTL to GDS, timing closure and deep-submicron issues.• Taped out SoC projects range up to 136 partitions, thousands of memories, 16nm technology with tracking records for successful SoC chips in volume production. • Known for delivering on schedule, highly motivated, and detail oriented.SKILLS• Frontend tools: Synopsys design compiler, Prime Time Analyzer, Conformal LEC, Spyglass CDC.• Backend tools: Cadence and Synopsys based physical design tools: First Encounter, ICC/ICC2 Compiler, Nanoroute, Star-RC, Simplex QX, Redhawk, Mentor Calibre, ICV.• FPGA tools: Synplify synthesis, Xilinx implementation.• Familiar with Perl, Make, Shell Script to automate and integrate the design flow.
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Implementation Design Engineer Contract At MetaSintegra Inc. Sep 2024 - PresentSanta Clara, California, UsASIC synthesis, floorplan and timing/linting/formal/CDC verification. -
Principle Physical Design EngineerMarvell Technology (Tanzanite Acquisition) May 2022 - Oct 2023Subchip-level implementation from RTL to GDS in 5nm technology.
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Physical Design Engineer Contract At GoogleSintegra Inc. Feb 2019 - Apr 2022Santa Clara, California, UsResponsible for physical synthesis RTL-to-netlist release and optimize floorplans during early chip design phase.• Enhanced and maintained Fusion/Design Compiler Topo Synthesis flow for new design technology.• Closely worked with architects, RTL and Physical designers for area, timing, constraints, power, and linting.• Designed and improved floorplan for synthesis to solve timing, congestion, and interconnect.• Conducted power reviews using PTPX from various simulation test vectors for power saving opportunities.
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Physical Design EngineerGlobal Unichip Corporation Na Jan 2018 - Jan 2019 -
Physical Design EngineerIntel Corporation Oct 2016 - Nov 2017Santa Clara, California, Us -
Physical Design EngineerCisco Aug 2010 - Sep 2016San Jose, Ca, Us• Developed CAD flow for Synopsys ICC/ICC2 P&R. Enhanced the flow for new features and tuned receipts for better quality of results. Contributed to team success by documented Wiki, supported, debug and resolved other experienced user issues. Conducted flow enhancement presentations and releases. Integrated the flow and interfaced with cross companies teams from EDA Synopsys/Cadence and ASIC foundries – Avago, Broadcom, Intel, TI, TSMC, and ST.• Implemented challenging timing and congestion SoC blocks from RTL to GDS using Synopsys DCG physical synthesis, ICC/ICC2 floorplanning, P&R, CTS, extraction, PT timing ECO closure, Redhawk, and ICV physical verification DRC/LVS.• Responsible for chip-level implementation using Cadence Encounter: power grid distribution; channel based repeaters place and route, timing closure, and physical verification.• Setup infrastructure: library installation, multiple sites data mirroring, cross-views checks, QA, disk usage monitoring. -
Asic Implementation EngineerCisco Sep 2002 - Aug 2010San Jose, Ca, UsCoordinated the physical design service activities with ASIC foundries and enhanced my program management and communication skills besides the following technical responsibilities.• Implementation responsibilities: DCG physical synthesis, define timing constraints and analysis, partition/floor plan, PT-PX power calculation, logic equivalent check, clock-domain-crossing check, and post-layout signoff timing.• Tool/flow responsibilities: Enhanced and support in-house synthesis as a highly integrated and automated top-down or bottom-up flow.• FPGA implementation using Synplify synthesis, Xilinx tools.
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SmtsProcket Networks (Acquired By Cisco) Aug 2000 - Sep 2002Implemented challenging timing and congestion SoC blocks from netlist to GDS. This startup was acquired by Cisco.
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SmtsArtx, Inc.(Start-Up) Acquired By Ati Research 1999 - 2000Santa Clara, California, UsImplemented challenging timing and congestion SoC blocks from netlist to GDS.
Willy Kuo Skills
Willy Kuo Education Details
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Stony Brook UniversityElectrical Engineering -
Chung Yuan Christian UniversityPhysics
Frequently Asked Questions about Willy Kuo
What company does Willy Kuo work for?
Willy Kuo works for Sintegra Inc.
What is Willy Kuo's role at the current company?
Willy Kuo's current role is Physical Design Engineer.
What is Willy Kuo's email address?
Willy Kuo's email address is wk****@****sco.com
What schools did Willy Kuo attend?
Willy Kuo attended Stony Brook University, Chung Yuan Christian University.
What are some of Willy Kuo's interests?
Willy Kuo has interest in Environment.
What skills is Willy Kuo known for?
Willy Kuo has skills like Asic, Physical Design, Verilog, Static Timing Analysis, Soc, Tcl, Perl Script, Shell Scripting, Fpga, Ic, Eda.
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