Developing “Signal in Space” IP.

• Own verification of fabric level designs (VCS, Verilog, ACE, Synplify, GLS) and porting of architectural tests to fabric level tests (Python, Make,). Generated tools for processing source code (Python, SystemVerilog) of tests and generating large tests for the FPGA containing multiple fabric level designs (all of the above)

Added QSFP(Xilinx), I2C, Bert, etc. Verilog RTL into the already existing Pico Framework for Deep Learning Accelerate PCIe cards. Developed C++ Software application for acceptance testing of existing and new features for the SB-855 PCIe card (follow on to SB-852).

•Own integration, timing closure (CDC), and ip development (Verilog/System Verilog) for video encoding/decoding, data encryption/decryption pipelines using Intel Altera Quartus Prime (Arria 10) and Mentor Graphics’ QuestaSim. Responsible for lab debug and bring up. Automation of lab testing on a per build basis. Converted AES GCM C-Model into a SystemVerilog DPI. and then UVM Agent. Developed additional UVM testbenches for other streaming components of the design.

I was hospitalized for 5 months with the flu which turned into pneumonia and then sepsis.Key Words: ECMO, Ventilator, PEG, MRI, any many other gross things.

Responsible for DisplayPort and MIPI high-speed interfaces on Xilinx ZYNQ UltraScale+ FPGA (Vivado) and development of software (SDK) to enable test-bed framework.

Responsible for TX/RX JESD channel capture, sample alignment, DDR Fetch/Store on Xilinx ZYNQ UltraScale+ FPGA under Vivado. Responsible for TX/RX JESD channel capture, sample alignment, DDR Fetch/Store on Xilinx ZYNQ UltraScale+ FPGA under Vivado. Performed Area, Performance, I/O, and Static Timing Analysis, CDC Analysis.

• Design FPGAs for Satellites. Responsible for Micro-Architecture and implementation of DSP and Systems Engineering requirements. Analyzed I/O, power, area, and Static Timing Analysis, CDC Analysis, Lint for each design.• Implemented Verilog RTL DVBS.2 Encoder for Virtex-4.• Performed SV/UVM Verification on Crypto Management Module (for RTAX).• Developed Verilog RTL fabric for managing AXI/Xilinx Aurora protocols and converting them into GD proprietary protocols (for Virtex-7). • Developed automation framework to import customer's RTL designs and provide quality metrics for feedback to GD and the customer.• Maintained LVDS SerDES Verilog RTL designs for new FPGA and ASICS.• Supported CAD tool development and training of new hires.

• CSE 320: Design and Synthesis of Digital Hardware: Design and synthesis of digital hardware with Verilog RTL hardware description language, computer-aided design tools, and programmable devices.• CSE 591: Advanced Hardware Systems Design: Application of Verilog RTL Hardware Design Languages (HDL) and Methodologies. HDL Verification Strategies, Techniques, and Methodologies. HDL Synthesis, Timing Closure, Place & Route, Pin Planning, and Post Synthesis Verification. This course focuses on using the Verilog RTL for Design and the SystemVerilog for verification.

[QUARK PRE-SILICON VERIFICATION ENGINEER] Responsible for verification of new features for the MinuteIA (Quark) processor.[ATOM POST-SILICON VALIDATION ENGINEER] Developed commercial OS debug applications to support hardware bring up on Android and Windows platforms (Windows KMDF). Owned DFX validation and bring up.· Completed development of C# library (Visual Studio 2013, SVN) for on-chip logic analyzer control software along with training and support (Agilent and Tektronix LA/Scopes). · Completed development of concurrency based testing framework (eCos, GIT) based upon in-house verification operating system for the Digital Home Group.· Completed development of automated register documentation repository (SystemRDL) to replace all register definitions normally found in HAS/MAS/etc.

Directed development team of six engineers in the company’s Nuclear Services Bureau, designing Class 1E safety and control systems for the next generation of nuclear power plants. Communicated with senior engineers and agents of the Nuclear Regulatory Commission, among others, to ensure on-time delivery of certifiable designs and documentation. • Completed eight Verilog RTL based FPGA designs responsible for measuring and controlling Nuclear Power Plant operation.• Successfully designed, verified and synthesized architecture for Verilog RTL based Hardware based Floating / Fixed Point Math engines and analog and digital (ADC / DAC) interfaces for FPGA-based platforms. • Debugged systems using logic analyzers (Agilent, Tektronix), calibrators (Fluke), and oscilloscopes.

EEE120: Digital Design FundamentalsDeveloped and taught VHDL based FPGA design curriculum. Lead two teams of students in the AVNET tech-games. These teams took 1st and 2nd place against the other community colleges.

• Designed hardware aimed at solving complex cryptographic mathematics problems for ITT’s Communications Systems section. Developed algorithms in Verilog, Java, and MATLAB; verified designs using System Verilog. Drove designs from start to verification of silicon. Directed software and validation engineers in the verification of ECC / RSA / DSA math engine.• Developed, integrated, and successfully tested Verilog RTL based Hardware RSA / DSA / ECC (binary and prime curves) encrypt / decrypt engine for ASIC. (United States Patent #8,521,793). Responsible for Synthesis (Design Compiler) Static Timing Analysis (Design Compiler/Prime Time), CDC Analysis, and Lint.• Owned integration, validation, and various VHDL RTL Hardware development (HDL-Designer) tasks of FPGA-platform-based radar signal processing system.• Owned Hardware development, verification (Questa-Sim), and Synthesis (Design Compiler) of ARC Processors and packet processing logic for ASIC Network Processor.

• Recruited to develop hardware for home cable television systems, working in the Consumer Electronics Group. Lead four software and hardware engineers in the development of hardware and testing software to validate various video decoders (H.264, MPEG-2, MPEG-4). • Developed Verilog RTL Video Synchronization Logic for displaying and controlling up to 32 channels on screen at once, and prototyped hardware and software (WinCE) for validation of Video Codecs and designs.• Modified Verilog RTL hardware-based stream-level MPEG-2 decoder to support slice-level decoding for a multi-format video decoder for Set-Top Box ASIC. Reduced gate count for product from 800,000 to 80,000, working with software team to offload hardware video decoding functionality onto re-configurable firmware-based video decoder engines.• Responsible for Synthesis (Design Compiler), Static Time Analysis (Design Compiler/Prime Time) Gate-Level-Simulation (Questa-Sim), and Formal Verification (LEC), CDC Analysis, and Lint of Video Codec engines

Developed architectural specifications for PCI (Peripheral Component Interconnect) Watchdog Timer and Flash Interface Unit for Embedded Systems ASIC. Partnered with designers and end-users to develop specs. Facilitated training courses.