Generated IP/SoC level Security Architecture reviews (threat modeling) for the next generationXeon family processors.Developed Security tool to deliver Register level Sanity for Xeon family and Desktop processors.Owns Security attribute registers for access level definition of all Server SoC.Crypto review, Security-Arch Contributor in hackathon of Security Engine IP and other IPs. Review security questionnaire per IP features, and Electronics design Specification for Xeonfamily.Automated the process of creating a guide for the programming of OS/OEM security registers.The representative of security in Xeon Feature development workforce.Strap/reset value owner across all Server SOCs.Architecture/micro-architecture and security review of Xeon Server’s new feature. Architecture feature understanding of SGX, Software Guard Extensions- A Trusted ExecutionEnvironment and other Security Technologies.North/South Security Engines. Architecture feature understanding of Secure boot, VTd, DFX, Trusted execution, PCI. Security Feature (SDL) review with Design.

Worked on GEM5, and LLVM compiler. Modeled scratchpad in gem5 (modular platform for computer system architecture research) to replace cache for multiprocessor systems. Worked on a software managed multi-core architecture. Through knowledge of memory hierarchy is required to perform cache replacement with scratchpad. Worked on LLVM compiler infrastructure to optimize loop for best use of scratchpad.

Computer Org/Assemb Lang Prog - CSE 230

Computer Architecture - CSE 420

• Development of Intel’s in house developed software to calculate the vulnerability of processor (AVF) to estimate the Soft Error Rate (SER).• Code development of Intel’s tool (to calculate AVF) for the Haswell architecture.• Automated the whole process of building and running Intel’s tool (to calculate AVF) using PERL.• Extracted the useful information using PERL regexp.

Architectural modification of LEON2,LEON3 microprocessor for error recovery; OS configured for leon2is RTEMS. Thorough knowledge of RTEMS is essential to avoid conflict between modified LEON2and RTEMS . Porting leon2 on ML403 (Virtex -4) board. Vhdl code is written with configuration file for targetVirtex-4. RTEMS simulations conducted with leon3 on TSIM simulator, and with GRMON Debugger onML403 ,ML507Board.

Pekoppa: Hardware Pro Arduino 5V, 3D Designing, Spinning Disc 3DTelevision: PIC microcontroller, PCB Prototyping Machine Eleven Auto,Schematic & Board Design, Power IC’s library designed in Eagle Cad Electrical Gear: PIC microcontroller, Laser Cutter Flashing Key Ring