Contact info: lpickup45@gmail.comAs a senior level electrical engineer, Lance is a strong team leader with expertise in developing ASIC design flows for the semiconductor industry. Most recently a member of the ASIC Timing Methodology team, he focused on setting up timing runs for low power applications using voltage islands for 32nm chips. Combining a novel power saving technique based on voltage scaling and statistical timing, Lance enabled technology for customers to signoff timing in a single run while achieving significant power savings.Lance is experienced in all aspects of ASIC design methodologies. As the IBM lead for reference flow development, he has worked with EDA partners from Cadence, Synopsys, Magma, Mentor and Apache to create state of the art RTL to GDS2 flows from 0.25um to 45nm. At each new node enhancements were added targeting hierarchy, low power, voltage islands, signal integrity and DFM.Lance has had success at growing entities from a concept and a small team to a successful business offering, particularly in cases where little is known at the outset. As a member of the initial team that rolled out the IBM ASIC offering, Lance developed an automated library generation and verification system and created the first front-end (synthesis, simulation, timing and test) flow. Based on this foundation, the business eventually grew into an industry leader with over $1B in annual revenue.Lance was also a member of the team that developed the first IP reuse guide and spec for IBM IP, enabling growth and monetization of internal IP. He created the simulation model creation section with a focus on VHDL to Verilog translation, model verification and IP protection. This was later extended to IBM Foundry clients by expanding the reuse methodology to back-end (GDS2 and LVS) models. Leading the IP publishing team, up to $8M in quarterly revenue was generated, a level achieved due to the significant amount of automation and organization of the team.