Lang Lin Email & Phone Number

Cupertino, Ca, Us

Research and product development for 3DIC mutilphysics simulation and hardware security.

San Jose, California

Triage chip/system power integrity issues and hardware security vulnerabilities with Ansys multiphysics solvers plus big-data platform.

San Jose, Ca

Support global semiconductor customers with Ansys simulation products in the areas of EMIR sign-off, power integrity methodology and reliability analysis flow. Drive new product evaluations for prospective customers for understanding feature needs. Research and apply distributed multi processing technologies to Ansys simulation flow to achieve the best accuracy and performance.

Cupertino, California, United States

Proposing and working on SBIR projects

Hudson, Massachusetts Area

- Microprocessor component design of data-path blocks and register file blocks with tasks of schematic creation, critical path simulation, power estimation, layout, static timing analysis, power optimization and ERC/DRC checks for sign-off quality.- Enabled an exhaustive methodology for full-chip-level power grid analysis of a large (over hundreds of million nodes) CPU design using vector-based dynamic power flow; scripting for the simulation and analysis flow to correlate with silicon power measurement results.- Scripting for post-silicon validation of microprocessor including test pattern generation, DFX collateral generation and PVT condition regression analysis.- Worked for Intel Federal LLC on design study of HPC processor.

Amherst

- Lead a team on a 45nm test-chip design and lab test of low-power chip unique ID generation circuit (PUF);- Power side-channel analysis of DES/AES cryptosystem: developed C/MATLAB program to analyze large amount of power supply current traces to extract key bits; experiences in using DPA workstation to demonstrate new attacks.- Explore a novel power modulation circuit to covertly convey bit information and demonstrate a statistical detection method to receive information. Published and co-authored one journal paper and six conference papers.

Hudson - Haifa

- High-volume manufacturing test of DDR IO TX/RX links for signal integrity, PDN/decap optimization and power supply noise tolerance; contributed to silicon-correlated model of DDR IO, power signal integrity- Lab work on electrical validation of high-speed differential QPI IO; scripting to create SSI/SSO patterns to stress power supply.

Phd, Electrical And Computer Engineering

Activities and Societies: VLSI circuits and systems group. Security and Privacy Research group.Dissertation: Cryptography Circuit Design.

M.S. 2006--2008, Electrical & Computer Engineering

Master Thesis: The Role of Leakage Power in Extracting Secrets from CMOS cryptosystems.

M.S, Eletronic Engineering

Work in the Key Lab of Quantum Information and Measurement. Project: Board-level design of base-band signal processor for optical/RF.

B.S, Electrical Engineering

Thesis: Low-power and robust design of an embedded wireless communication system. "A special logic analyzer", winning the top Design Award.

Education record