Larry Pham Email & Phone Number

Fremont, Ca, Us

Norwalk, Connecticut, Us

Provided process and quality engineering support for production in Asia to maintain yield targets at 99%.Implemented cost reduction, process improvements and process cycle time reduction for existing and new product introduction (NPI).Performed component to circuit to system level root cause analysis on existing and NPI to prevent and reduce manufacturing and reliability issues as part of the team’s continuous improvement efforts.Worked with engineers from all disciplines across the organization with investigation, troubleshooting and resolution of mechanical, electrical and process related failures.Experienced with collecting data, analyzing results, design experiments in order to qualify new parts or process changes.Worked closely with design engineers on the Taipan 1 program by providing failure analysis and design for manufacturing (DFM) support from design to manufacturing to mass production to an overseas contract manufacture.Designed a new Printer Test board from schematic to tapeout in order to improve testing capability for NPI. The design led to a patent submission. Patent 8319501 Optical Component Identifier; Components on a circuit board can be identified by light sources in response to a variety of conditions.Redesigned a current production Printer Head Driver board by utilizing a new Xerox developed ASIC for next generation design. The redesign was completed on schedule with a projected annual cost saving of $922K.Developed an improved script to increase efficiency by 50% for a printer assembly process. Qualification and reliability testing were completed on schedule with a projected annual cost savings of $900K.Developed a comprehensive failure analysis procedure for NPI to train engineers and technicians in Production regarding component, PCB assembly and system level failure analysis. One case reduced the ASIC failures from 19% to <1% by correctly identifying the root cause.

Vancouver, Wa, Us

Performed Microsoft WHQL, compatibility, ad hoc and localization testing for clients.Appointed to work with client on-site, Welch Allyn; Provided quality assurance for the Acuity software for various patient monitors.

Beaverton, Or, Us

Designed USB to SPI Host device that reduced an evaluation kit cost. The design was also embedded in the FPGA test platform. Lead engineering of the complete project from specifications, developing firmware, schematic, and PCB layout to testing, verification, and tapeout.Designed SPI bus protocol Bus Functional Model (BFM) in Verilog as part of a FPGA test platform. BFM was used as a proprietary test tool to burn EEPROMs, verify the on-chip SPI bus protocol, and to debug both firmware and hardware.Performed ASIC and firmware verification using the FPGA test platform by developing and running test scripts.Supported firmware debug on the FPGA test platform by performing RTL builds, setting up the TLA, and executing scripts to test the ASIC.Managed the automated regression suite by developing test scripts in Python that verifies on-chip functionality for new RTL and firmware builds before they are checked into the repository.

Appointed project lead in the Networking Management Lab in the Spring of 2005.Worked in a team to execute test packages on networking platforms.Document bug reports and write/proof-read various testing methodologies.Provide fast and accurate quality-control results with excellent documentation for clients.

Master'S Degree, Engineering Management

Education record

Bachelor'S Degree, Electrical Engineer