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Larry Zu, Ph.D. personal email
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Larry Zu is the founder and CEO of Sarcina Technology LLC in Palo Alto, California. His company designs advanced semiconductor packages to achieve first tape-out success through rigorous chip-package-board co-design and co-simulation. He also specializes in product engineering for wafer and assembly yield enhancement, Q&R, and supply chain management. Since its inception in 2011, Larry has grown Sarcina from designing packages for a few small companies to doing package designs for several top semiconductor companies in the world. As of today, all his company's package design tape outs are first-time successes. Since then, he has expanded his company to wafer probing/final test hardware and software development as well as turnkey service.Larry is an industrial veteran with experience from Bell Labs, DEC, Intel, and TSMC where he worked on products such as the Alpha, Itanium 2, Pentium 4, and XBOX 360 microprocessors. Over his career, he has taped out nearly 1000 packages with >99% first-time tape-out success rate.Larry received his B.S. in physics from Peking University and his Ph.D. in electrical engineering from Rutgers University. He has many refereed IEEE publications and holds multiple US patents which have been used in leading US companies' key products.
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Chief Executive OfficerSarcina Technology Llc Jun 2022 - Present -
PresidentSarcina Technology Llc Oct 2011 - Jun 2022• One-stop turnkey service: wafer-in, chip-out.• Our customer includes world’s top 10 semiconductor company, world’s top 10 software IT company, large system company, ASIC design service company, medical equipment company, and high-flying startup in Silicon Valley and across the US.• High performance, high pin count, and high power semiconductor package design.• Low cost RF package design.• SiP, MCM, and 2.5D Si interposer package design.• Power/signal integrity channel sim with chip, package, & PCB for >56G SerDes and >3G DDR4.• We have successfully taped out many packages, all first time success.• Probe card design, simulation and fabrication for RFIC and ASIC SoC.• Final test loadboard, socket, and change kit design, simulation and fabrication for RFIC, ASIC SoC, SiP, MCM and 2.5D Si interposer.• Translate WGL, STIL, and EVCD test vectors to ATE test programs for multiple test platforms.• Engineering debugging of test hardware and software from prototyping to production.• Production wafer probing, assembly and final test service.• Product qualification. • Logistic handling, supply chain management and RMA in production.
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Senior Director Of Engineering & Business DevelopmentGuc May 2007 - Nov 2011Hsinchu Science Park, TwSemiconductor product engineering for world's No.1 networking company.• Managed products’ revenue is about US$0.5B over their lifetime • Doubled or tripled wafer yield in <18 months for all chipsets• Q&R and supply chain management from prototyping to production• Semiconductor packaging. Built a packaging team from scratch• Package design,• Electrical co-simulation for core, SerDes, DDRx, and RF• Thermal co-simulation• DFM, DRC, and LVS for package layout• Successfully taped out ~500 packages with >99% first time successful rate.• Business development worldwide -
Gpu Package Design And Program ManagementTsmc Jul 2006 - Mar 2007Hsinchu, Taiwan, TwXbox 360 GPU MCM package design. Reduced substrate layer count from 8 to 6 by routing 1100 I/Os on a single layer. Significant cost reduction. -
Engineering ManagerIntel Corporation Jul 1998 - Apr 2006Santa Clara, California, UsMicroprocessor package design, layout, and electrical simulation for Itanium 2, Pentium 4, and Xeon.10G transponder and transceiver design and product engineering.RF front-end module design and testing for 802.1 a/b/g using MCM-D & MCM-L (Laminate) technology. - EM simulation, design, layout, wafer probing, testing, analysis - Balan, filter, LNA, PA, diplexer, switch -
Senior EngineerDigital Equipment Corporation Jan 1996 - Jun 1998Microprocessor package design and PI/SI simulation for 21264 (EV6).Performance improvement from a wirebond 21164 (EV5) package to a flip-chip package.
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Ph.D. CandidiateRutgers University 1992 - 1996New Brunswick, Nj, UsMajored in Electrical and Computer Engineering -
ConsultantAt&T Bell Laboratories Feb 1992 - Dec 1995Holmdel, New Jersey, UsMCM-D flying probe test equipment automation.Integrating high Q-factor RF inductor on MCM-D. - Design, EM simulation, wafer processing, testing, & analysisIntegrated Passive Device (IPD) on MCM-D
Larry Zu, Ph.D. Skills
Larry Zu, Ph.D. Education Details
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Rutgers UniversityElectrical And Computer Engineering -
Peking UniversityPhysics
Frequently Asked Questions about Larry Zu, Ph.D.
What company does Larry Zu, Ph.D. work for?
Larry Zu, Ph.D. works for Sarcina Technology Llc
What is Larry Zu, Ph.D.'s role at the current company?
Larry Zu, Ph.D.'s current role is CEO, Sarcina Technology LLC.
What is Larry Zu, Ph.D.'s email address?
Larry Zu, Ph.D.'s email address is la****@****hoo.com
What schools did Larry Zu, Ph.D. attend?
Larry Zu, Ph.D. attended Rutgers University, Peking University.
What are some of Larry Zu, Ph.D.'s interests?
Larry Zu, Ph.D. has interest in Science And Technology, Education.
What skills is Larry Zu, Ph.D. known for?
Larry Zu, Ph.D. has skills like Semiconductors, Asic, Soc, Ic, Signal Integrity, Serdes, Engineering Management, Semiconductor Industry, Product Engineering, Eda, Mixed Signal, Analog.
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