Larry Zu, Ph.D.
AeroLeads people directory · profile

Larry Zu, Ph.D. Email & Phone Number

CEO, Sarcina Technology LLC at Sarcina Technology LLC
Location: Palo Alto, California, United States 8 work roles 2 schools
1 work email found @sarcinatech.com LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email l****@sarcinatech.com
LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
Role
CEO, Sarcina Technology LLC
Location
Palo Alto, California, United States

Who is Larry Zu, Ph.D.? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Larry Zu, Ph.D. is listed as CEO, Sarcina Technology LLC at Sarcina Technology LLC, based in Palo Alto, California, United States. AeroLeads shows a work email signal at sarcinatech.com and a matched LinkedIn profile for Larry Zu, Ph.D..

Larry Zu, Ph.D. previously worked as Chief Executive Officer at Sarcina Technology Llc and President at Sarcina Technology Llc. Larry Zu, Ph.D. holds Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering from Rutgers University.

Company email context

Email format at Sarcina Technology LLC

This section adds company-level context without repeating Larry Zu, Ph.D.'s masked contact details.

{first}@sarcinatech.com
86% confidence

AeroLeads found 1 current-domain work email signal for Larry Zu, Ph.D.. Compare company email patterns before reaching out.

Profile bio

About Larry Zu, Ph.D.

Larry Zu is the founder and CEO of Sarcina Technology LLC in Palo Alto, California. His company designs advanced semiconductor packages to achieve first tape-out success through rigorous chip-package-board co-design and co-simulation. He also specializes in product engineering for wafer and assembly yield enhancement, Q&R, and supply chain management. Since its inception in 2011, Larry has grown Sarcina from designing packages for a few small companies to doing package designs for several top semiconductor companies in the world. As of today, all his company's package design tape outs are first-time successes. Since then, he has expanded his company to wafer probing/final test hardware and software development as well as turnkey service.Larry is an industrial veteran with experience from Bell Labs, DEC, Intel, and TSMC where he worked on products such as the Alpha, Itanium 2, Pentium 4, and XBOX 360 microprocessors. Over his career, he has taped out nearly 1000 packages with >99% first-time tape-out success rate.Larry received his B.S. in physics from Peking University and his Ph.D. in electrical engineering from Rutgers University. He has many refereed IEEE publications and holds multiple US patents which have been used in leading US companies' key products.

Listed skills include Semiconductors, Asic, Soc, Ic, and 19 others.

Current workplace

Larry Zu, Ph.D.'s current company

Company context helps verify the profile and gives searchers a useful next step.

Sarcina Technology LLC
Sarcina Technology Llc
CEO, Sarcina Technology LLC
AeroLeads page
8 roles · 35 years

Larry Zu, Ph.D. work experience

A career timeline built from the work history available for this profile.

President

• One-stop turnkey service: wafer-in, chip-out.• Our customer includes world’s top 10 semiconductor company, world’s top 10 software IT company, large system company, ASIC design service company, medical equipment company, and high-flying startup in Silicon Valley and across the US.• High performance, high pin count, and high power semiconductor package design.• Low cost RF package design.• SiP, MCM, and 2.5D Si interposer package design.• Power/signal integrity channel sim with chip, package, & PCB for >56G SerDes and >3G DDR4.• We have successfully taped out many packages, all first time success.• Probe card design, simulation and fabrication for RFIC and ASIC SoC.• Final test loadboard, socket, and change kit design, simulation and fabrication for RFIC, ASIC SoC, SiP, MCM and 2.5D Si interposer.• Translate WGL, STIL, and EVCD test vectors to ATE test programs for multiple test platforms.• Engineering debugging of test hardware and software from prototyping to production.• Production wafer probing, assembly and final test service.• Product qualification. • Logistic handling, supply chain management and RMA in production.

Oct 2011 - Jun 2022

Senior Director Of Engineering & Business Development

Guc

Hsinchu Science Park, Tw

Semiconductor product engineering for world's No.1 networking company.• Managed products’ revenue is about US$0.5B over their lifetime • Doubled or tripled wafer yield in <18 months for all chipsets• Q&R and supply chain management from prototyping to production• Semiconductor packaging. Built a packaging team from scratch• Package design,• Electrical co-simulation for core, SerDes, DDRx, and RF• Thermal co-simulation• DFM, DRC, and LVS for package layout• Successfully taped out ~500 packages with >99% first time successful rate.• Business development worldwide

May 2007 - Nov 2011

Gpu Package Design And Program Management

Hsinchu, Taiwan, Tw

Xbox 360 GPU MCM package design. Reduced substrate layer count from 8 to 6 by routing 1100 I/Os on a single layer. Significant cost reduction.

Jul 2006 - Mar 2007

Engineering Manager

Santa Clara, California, Us

Microprocessor package design, layout, and electrical simulation for Itanium 2, Pentium 4, and Xeon.10G transponder and transceiver design and product engineering.RF front-end module design and testing for 802.1 a/b/g using MCM-D & MCM-L (Laminate) technology. - EM simulation, design, layout, wafer probing, testing, analysis - Balan, filter, LNA, PA, diplexer, switch

Jul 1998 - Apr 2006

Senior Engineer

Digital Equipment Corporation

Microprocessor package design and PI/SI simulation for 21264 (EV6).Performance improvement from a wirebond 21164 (EV5) package to a flip-chip package.

Jan 1996 - Jun 1998

Ph.D. Candidiate

New Brunswick, Nj, Us

Majored in Electrical and Computer Engineering

1992 - 1996 ~4 yrs

Consultant

Holmdel, New Jersey, Us

MCM-D flying probe test equipment automation.Integrating high Q-factor RF inductor on MCM-D. - Design, EM simulation, wafer processing, testing, & analysisIntegrated Passive Device (IPD) on MCM-D

Feb 1992 - Dec 1995
2 education records

Larry Zu, Ph.D. education

Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering

Rutgers University

Bs, Physics

Peking University
FAQ

Frequently asked questions about Larry Zu, Ph.D.

Quick answers generated from the profile data available on this page.

What company does Larry Zu, Ph.D. work for?

Larry Zu, Ph.D. works for Sarcina Technology LLC.

What is Larry Zu, Ph.D.'s role at Sarcina Technology LLC?

Larry Zu, Ph.D. is listed as CEO, Sarcina Technology LLC at Sarcina Technology LLC.

What is Larry Zu, Ph.D.'s email address?

AeroLeads has found 1 work email signal at @sarcinatech.com for Larry Zu, Ph.D. at Sarcina Technology LLC.

Where is Larry Zu, Ph.D. based?

Larry Zu, Ph.D. is based in Palo Alto, California, United States while working with Sarcina Technology LLC.

What companies has Larry Zu, Ph.D. worked for?

Larry Zu, Ph.D. has worked for Sarcina Technology Llc, Guc, Tsmc, Intel Corporation, and Digital Equipment Corporation.

How can I contact Larry Zu, Ph.D.?

You can use AeroLeads to view verified contact signals for Larry Zu, Ph.D. at Sarcina Technology LLC, including work email, phone, and LinkedIn data when available.

What schools did Larry Zu, Ph.D. attend?

Larry Zu, Ph.D. holds Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering from Rutgers University.

What skills is Larry Zu, Ph.D. known for?

Larry Zu, Ph.D. is listed with skills including Semiconductors, Asic, Soc, Ic, Signal Integrity, Serdes, Engineering Management, and Semiconductor Industry.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.