Larry Layton Email and Phone Number

Supported physical verification portions of foundry PDKs at various node point for Microchip internal customers.

Coordinated tool presentation and implementation and troubleshooting between customers, sales, and R&D. Represented multiple Cadence tools to customers, including Assura, PVS, Dracula, and VIPVS in physical design space, LPA, CMP, and LEA in DFM space, QRC in extraction space, and Voltage Storm for IR/EM analysis.

Applications Engineer supporting Physical Verification and Extraction products (Hercules and StarRC).

Responsible for implementation and updates to DRC/LVS tools used at worldwide CSIC groups within Motorola, including rule deck development, job submission scripting and internal training on physical verification tools suite. Developed and delivered User training to 8 worldwide Motorola design centers.

Manage a team of layout designers responsible for autorouting of Atari chipsets. Responsible for determining methodologies and implementation.

Layout work on Calma systems and then transitioned to autorouting using Silvar-Lisco GARDS software. Worked on multiple DSEG chips for VHSIC projects.

Electronic technician working on board, unit, and systems level testing of radar display units for military aircraft. Responsible for burn-in environmental testing area on second shift.