Laura Risner Email & Phone Number

Supervise department of 4 engineers and 7 specialists, driving all goals and activities as well as employee career development and ensuring cost-effective utilization of laborDesign process qualifications of new technologies and devices, working with process engineering to identify correct electrical parameter control limits and center those parameters for Cpk improvement.Sustain EDS Out Gate microscopic inspection as the last check for quality of SAS productCoordinate and interpret Gate Oxide Integrity and High Temperature Stress testing of DRAMRespond to internal and external customer claims with root cause, corrective actions and resultsEvaluate back-end yields and effects of various fabrication issues on back-end yieldsOrganize and run Material Review Boards in response to fab events which could impact product, and drive actions to test and contain affected productScrutinize proposed fabrication changes for potential quality impacts before approval/disapproval during Change Control BoardsAccomplishmentsCompleted a 6 Sigma project which reduced cycle time of QA inspection by 33% over 4 months.Eliminated chronic device pad-staining issues by isolating the cause to an interaction of packing materials and environmental conditions during shipping. Evaluated and contracted for new shipping foam.Principal Failure Analysis Engineer 2002Held sole responsibility for one DRAM product line, reviewing every test wafer map daily, identifying chronic and new yield loss signatures, electrically testing die to pinpoint defect location and characteristicsResponsible for identifying root cause of zero-yield wafers for all devices and driving fixes to prevent future zero-yield.AccomplishmentsDue to heavy zero-yield losses from misaligned photolithography at metal layers, drove increased 100% wafer inspection at process weak points, which led to faster feedback and clearer information that ultimately resulted in eliminating 80% of misalignments.

Managed 40+ yield engineers, technicians and specialists.Implemented defect monitoring systems using KLA 2135s with statistically sampled manual defect classification to monitor the entire process line with extremely quick feedback. Built strong relationships with process engineering departments to drive quick responses and fixes for defect sources. Also supported process engineering requests for special monitors during process changes or yield improvement projects.AccomplishmentsCharacterized a unique worm-like defect signature using inline inspection, used DOE to reproduce interactions causing the problem, and worked with a cross-functional team to identify and fix a plasma etch/wafer scribe damage issue that improved yields on the 0.19um DRAM device by 5%.

As an original member of Samsung Austin's process/device task force team, spent 9 weeks in Korea acquiring process and device information for the Fab 1 startup in Austin.

Implemented full-loop defect monitoring system at startup of 0.65 um lines, integrating advantages of Tencor 7600 and KLA 2130 to drive an accelerated yield ramp. Collaborated with electrical test to match bitmapped SRAM failures to KLA/Tencor defect sites for improved understanding of killer defect sources.Intermediate Process Engineer, Feed-forward Yield

Responsible for electrical test/sort disposition and failure analysis on low yielding lots for ASIC, Gate Array, and Logic devices.