Lawrence Cooper Email & Phone Number

Kirkland, Wa, Us

Kent, Wa, Us

Avionics Engineering Team Lead: Managed cross-functional engineering teams supporting New Glenn, New Shepard and Blue Engines avionics hardware development and qualification.> Q3 2021 to Present: *New Glenn Avionics, Director Hardware Engineering* a cross-functional hardware engineering team supporting FPGA, electrical, mechanical and manufacturing engineering development solutions, processes and procedures.> Q2 2019 thru Q3 2021: *New Glenn Avionics, Director Embedded Controls* an Integrated Product Team developing New Glenn Avionics Embedded Controls solutions; hardware, software and firmware. Led team thru successful Preliminary Design Review and preliminary product solution demonstrations and hardware Final Design Review. Team developed qual-ready embedded controller product solutions.> Q2 2018 thru Q2 2019: *New Glenn Avionics Stage 2 Principle Manager* for Integrated Product Team developing New Glenn Avionics Embedded Controls Hardware. Led team to successful Concept Design Review and proto HW development. Led team staffing to ~100% growth into 2019.> Q1 2017 thru Q2 2018: *Avionics HW Team Manager* for 23-person cross-functional engineering team providing matrixed support to New Shepard, New Glenn and Engines product teams. Released updated Blue Origin corporate avionics Hardware Development Plan aligning with DO-254. Led avionics engineering team staffing to ~10% growth in 2017.

Santa Clara, California, Us

Staff Platform Application Engineer: Led cross-functional/geographical/organizational team supporting OEM customer High Performance Computing (HPC) platform development based on the Intel Xeon Phi™ processor.Customer technical marketing representative: Developed/delivered technical messages; drove issue resolution; aligned customer design, power-on and debug needs with product development direction and schedules.Hardware design collateral development lead: Aligned/consolidated customer facing engineering design models, product datasheets, and thermal-mechanical, electrical and architectural design specifications.On-site customer technical training lead: Developed/presented HPC platform hardware design collateral related to Intel Xeon Phi™ processor socket and associated thermal-mechanical processor retention hardware.

Hillsboro, Or, Us

Senior Client Hardware Engineer: Led Personal Computer (PC) client memory power analysis; researched vendor memory power capability trends; aligned design performance, cost and schedule targets across client product roadmap. Analyzed and validated compute platform low-power memory performance; traffic across workloads and thermal design point and connected-standby power targets; aligned client memory power budget.Senior Processor Substrate Design Responsible Engineer: Headed cross-functional performance and mainstream client processor FCLGA substrate design team; met performance, cost and schedule targets for PC Client Group products roadmap. Led design team from concept to tapeout for multiple generations of CPU products.*Received Division Recognition Award for layer count reduction and polymer TIM cost savings.**Led 1st Xeon Phi™ multicore GPU FCBGA substrate development effort from concept to successful tapeout, Received Division Team Award for cross-function / cross-organization leadership.*Senior Technical Program Manager: Led Desktop Client Product Showcase and Recommended Material List projects from concept definition to delivery of fully functional demo systems for CES.

Santa Clara, California, Us

System RTL Model Build Lead Engineer: Developed and maintained (cluster, component, system and cosimulation)-level VHDL models and simulation environment for Intel's enterprise class server chipset multi-site cross-functional concurrent pre/post silicon design/validation efforts.*Enabled concurrent validation of 42+ platform architectures, ~4x over prior generation capability, allowing validation team to pull-in bug identification and resolution schedule.*Directed feature-based, random, and co-simulation regressions against latest RTL models. Tracked compute resource allocation/utilization and led junior engineers and interns in debug prioritization.

Santa Clara, California, Us

Led hardware design, integration, validation (environmental and regulatory qualification), and documentation (BOMs, FAI’s, etc.) for low-profile and thin-line desktop computers.*Designed, validated and qualified superior desktop CPU heat sink and thermal interface material reducing cost by 50% ($4 per system) and improving performance by 5 C over existing solutions.*Spearheaded innovative division-wide process improvement efforts to advance thermal and acoustic design and test capabilities. Co-authored acoustic and thermal test procedures for division-wide product qualification, and co-developed innovative environmental validation test processes for small form-factor computers.*Led effort to build world-class acoustic test chamber (noise floor >5dB below prior corporate capability), effort recognized and promoted in quarterly Intel corporate-wide process innovation video.*

Co, Us

Course Director for technical core "Introduction to Linear Algebra and Differential Equations" course. Staff Instructor for "Advanced Engineering Mathematics" for the French Cadet Exchange Program, "System Dynamics" for the Aerospace Engineering Department, and "Differential and Integral Calculus".*Selected Department of Mathematics Company Grade Officer of the Quarter.*

Technology Program Manager and Controls Engineer for advanced DOD laser and optics stabilization and pointing programs.System Design Engineer, led environmental and reliability requirements definition and testing for advanced USAF programs.*Selected laboratory Company Grade Officer of the Quarter.*

Bachelor’S Degree, Mechanical Engineering

Master’S Degree, Electrical And Electronics Engineering

Master Of Business Administration (M.B.A.), Technology And Innovation Management