Puneet Bhatia Email & Phone Number

Bengaluru, KA, IN

Bengaluru, Karnataka, India

Working in the Wireless LAN technology in the scope of PHY RTL Development.

Bengaluru, Karnataka, India

Working in the Wireless LAN technology in the scope of PHY RTL Development.Responsible for new feature addition in Rx Frequency Domain for 802.11BE including but not limited to area improvements, performance improvements and power optimizations.Also had people management responsibilities with team size of upto 7 members.

Worked as PHY Lead for various wired modem technologies (DSL, DOCSIS), overall responsible for delivery of PHY RTL which is functionally clean meeting all functional and timing requirements. Responsible for micro-architecture, RTL Implementation and support for Synthesis, STA and post-silicon bringup.Co-ordinating and interfacing between cross-functional.

Bengaluru Area, India

Worked as PHY Lead for various wired modem technologies (DSL, DOCSIS), overall responsible for delivery of PHY RTL which is functionally clean meeting all functional and timing requirements. Micro-Architecture, RTL Implementation and support for Synthesis and STA. Interfacing between 3rd party vendors and cross-functional teams.

Bangalore

Worked on OTN Mega Chip Digi. Module owner for GMP Transmit side block with responsibility of Micro-Architecture definition, RTL Coding, Linting CDC and other flows. Role also included in supporting the verification team and the FW team.Worked Storage Chip DMA involving design tweak for performance optimization, power optimization, constraint generation.

Core Member of the SoC/IP Team. Responsibilities ranging from conceptualization of IP, Design, Verification. Synthesis, STA and Power Analysis for Multi-million SoCs. Managing fresh teams to understand the ASIC cycle, exposing them to various communication protocols like USB. Backend work pre-sales for ASIC/FPGA Marketing.

Core Member of the SoC/IP Team. Responsibilities ranging from conceptualization of IP, Design, Verification. Synthesis, STA and Power Analysis for Multi-million SoCs. Managing fresh teams to understand the ASIC cycle, exposing them to various communication protocols like USB. Backend work pre-sales for ASIC/FPGA Marketing.

Working in Front End VLSI Design and Verification. e-Specman based HVL verificatoin in USB 2.0 IPs and integrating them in the SoC. Timing Closure and Synthesis, both the at the IP level and the SoC level.

Master Of Technology - Mtech, Microelectronics

Dvlsi, Semiconductors

Bachelor Of Technology (B.Tech.), Electronics And Communication Engineering