Louis Ledoux Email & Phone Number

I am currently completing my PhD at the Universitat Politècnica de Catalunya / Barcelona Supercomputing Center, specializing in computer architecture with a focus on arithmetic hardware designs and floating-point operations. My research encompasses high-performance computing (HPC), silicon design, floating-point formats/representations/circuits, GEMM/MMM kernels, and integrating these with software frameworks such as PyTorch, NumPy, and BLAS.With a foundational background in FPGA acceleration, I have honed my skills in testing designs through software/hardware co-design, utilizing FPGAs in the cloud and Acceleration/FPGA as a Service (AaaS/FaaS) platforms like AWS F1 instances. For instance, I have achieved real-time HDR video rendering from several SDR streams, saturating PCIe links for efficient SSD NVMe roundtrip processing.My PhD work has primarily focused on inventing mechanisms to budget precision and accuracy at the hardware level according to workload numerical requirements. For example, AI applications may require a 5-bit internal datapath, whereas sea surface height calculations might need around 100 bits. This research has resulted in the generation of numerically tailored HPC GEMM kernels for FPGA and ASIC, culminating in a tapeout and several publications.More recently, my work has shifted from trading energy efficiency for accuracy to focusing on trading performance for area (space and time), a crucial aspect of the vector processing paradigm.Additionally, I am an active contributor to the open-source silicon community, developing and sharing code to foster innovation and collaboration. My contributions include open-source ASIC flows for extensive design space exploration with automated reporting for publications.