Enthusiastic in Hardware Root of Trust (RoT) powered by PUF technology providing silicon Inborn Identity in trusted supply chain. Pursuing the hardware wallet technology for CBDC applications based on the hardware RoT, and also the anti-counterfeiting technology for printer cartridges, ink toners, laptop batteries, and other general consumer products which are the long time problem in the industry. As an IoT security professional, I also work on bringing security features to network components such as Serial to Ethernet, LoRa network, Smart IoT sensors, Industrial IoT, and FIDO applications.

The world first SoC chip that extracts 3D depth images from a single camera! It employs the Dual Aperture Technology that uses 4-color CMOS image sensor (RGB+IR) to evaluate the depth of an object. It is amazing technology that enables small form factor of camera and no IR emitter required. • Managing SoC team to develop 4-color CMOS image sensor SoC chip which extracts 3D depth image from a single camera based on Dual Aperture Technology.• Developed (patented) the regularization algorithm to make full depth image out of the edge based depth image.• Worked on IoT security SoC chips (FIDO/U2F/UAF applications) especially at power saving scenarios.• 4 Tape outs to TSMC/GF/Fujitsu fabs for the SoC chips, and successfully brought up E/S’s.• Managed Productization team for packaging, silicon bring up and Qual processes.• Developed low power SoC design flows using cpf/upf methodologies in the multiple power domain chips.• Managed back-end design processes (i.e. automatic place and route process) through an out-sourced design house.• Led Verification IP team to verify SDIO master IP towards the IoT security chip tape-out

Methodology Leader in Custom Circuit Design for FPGA.RTL logic designs:• Architected and implemented CRAM (configuration RAM) RTL models and its fullchip test schemes in FPGA configuration designs in 20nm project• Wrote an automatic verilog testbench development tool for IP blocks, and led entire engineering team to complete the IP and fullchip configuration models• Wrote verilog models of Logic Element in FPGA core fabric• Developed a flow for extracting CRAM mapping information, and wrote extensive TCL programs to perform RTL tracing under StarvisionPro• Developed methodologies for formal verification flow using both LEC and ESP-CV engines to perform equivalence checks for FPGA core fabric IPs and memory blocksASIC and Physical Designs:• Experienced in semi-custom library flow development in 14nm Trigate FinFET technology• Developed a LUT (Lookup table) Logic Element block in FPGA chip using synthesis tool (DC-topo) and completed the design using PnR tool (ICC)• Wrote verification flows for voltage multi-domain crossings at fullchip level using Perl and TCL• Developed a formal verification flow using ESP-CV and led IP design team• Developed a methodology of high voltage spacing rules for FPGA chip designs in TSMC's 28nm technology, and drove the IP design teams and the design automation team for successful tape out deliveries of Stratix 5 and Arria 5.• Led design team to perform static checks (SchERC and PERC) for the custom IP blocks• Developed a methodology of device integrity check flow and associated multiple power domain handling flow in 28nm technology, and led CAD and IC design team to complete the implementation.• Cross functional leader, interacting with IP and Product design teams, layout team, and CAD team in both San Jose and Penang R&D sites to resolve issues and achieve the team goals. Successfully achieved 28nm/20nm project tapeouts to TSMC

[Sr. Circuit/Asic designer]• Developed Timing methodology using Einstimer in cu45 IBM SOI technology. • Wrote TCL scripts to bring up Einstimer flows (statistical timing tool) and wrote ECO scripts (cap fix, slew fix, and timing fix)• Clock tree design and OCV/skew analysis in TSMC 40nm technology

contracting on custom memory block design (mmtlb, fifo) and glitch free clock mux design used in a DVFS system. Also completed on automatic swapping flow for combo-flops using Perl.

[Custom circuit design and physical design manager]• Designed a 2R1W 32KB and a 2R2W 4KB register files at TSMC 65GP tech node• Designed a glitch free clock mux for at-speed clock controls for macrotest• Designed low pass and band pass filters for board level signal filtering • Managed a circuit and layout team for designing custom multi-ported memories• Brought up back-end EDA tools from scratch such as Hsim, Hspice, Virtuoso, innologic, Laker and ADP, etc. • Main contact to TSMC 65GP to determine technology nodes and IO libraries • Worked as a contact engineer to packaging company (ASE/ISE) • Owner of Sidense OTP (one time programmable) ROM and TSMC eFuse implementation• Wrote verilog testbenches to bring up the embedded OTP macro in the video chip• Managed a DFT team for mbist insertions (using Virage SMS) [Flow automation expert in ASIC backend designs]• Developed a timing model (.lib) generation tool for custom blocks using Perl skills• Designed dynamic flip flops, and developed a flop characterization flow• Wrote TCL flows for assigning design constraints (sdc file) for Synopsys tools (Prime Time and DC-topo).• Assigned TSMC IO pads to the chip IO and did package and board level simulations• Managed an outsourced ASIC PnR company to complete the chip development

Custom circuit designer, Technical leader of register file team.• Project involved: Ultra-sparc III, VI, VI+, and recent processors. • Technical leader in a custom circuit and register file design team. • Developed the ECDF (Effective clock delayed flops) flow using Perl for maxtime solution, and led the design teams to add it to designs • Developed the circuit design methodology and led the circuit group to achieve the design quality and schedule • Established the design review/sign-off processes and design quality check processes, and led the team to accomplish the tape out goals • Completed 6 tape-outs throughout 5 independent projects • Dynamic adder design in the circuit side • Full custom designs of the working and architectural register file (7R5W). • Clock headers, Flip-flops, and Floating Point Register File designs. • Memory cell design and characterizations for register files using statistical method. • SRAM design: single/dual port cell design, single-ended sense amp, valid-load/store prediction array in I-cache unit • DFM (Design for Manufacturability) leader, and layout methodology leader. • SERDES project: Completed a phase interpolator design in CDR block.

Full custom circuit designer• Project involved: the world first GHz Power-PC microprocessor development. • VHDL logic design and simulations for LZA (Leading Zero Anticipator), CU (Compare Unit), etc • Full custom dynamic circuit and layout design for LZA, CLZ, CU, etc • Whole chip functional verification (using IBM tool Genie/Genisys) • Scan chain control design and verification for the whole chip • Project involved: Developed the world first Giga-Hertz PowerPC integer microprocessor • Design a new inductor device operating in high-freq (3-5 GHz) LC oscillator. • Functional Verification of the microprocessor using RTPG technique • Developed the phase accurate VHDL models for all the macros. • Developed all the test cases to test the GHz processor