Lejun Wang Email & Phone Number
@analog.com
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Who is Lejun Wang? Overview
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Lejun Wang is listed as Packaging Engineer at Allegro MicroSystems at Allegro MicroSystems, based in Wilmington, Massachusetts, United States. AeroLeads shows a work email signal at analog.com and a matched LinkedIn profile for Lejun Wang.
Lejun Wang previously worked as Sr. Principal Packaging Engineer at Allegro Microsystems and Semiconductor Packaging Engineer at Analog Devices. Lejun Wang holds Ph.D., Materials Science & Engineering from Georgia Institute Of Technology.
Email format at Allegro MicroSystems
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AeroLeads found 1 current-domain work email signal for Lejun Wang. Compare company email patterns before reaching out.
About Lejun Wang
- 20+ years of experience in electronic packaging industry in NPI, Design for Manufacturability and Reliability (DFX), technology development, process characterization/qualification, statistical data analysis, structured problem solving, FMEA, PFA, CPI, DOE, SPC, and lean sigma manufacturing for mobile products and high reliability electronic modules in medical devices and CPU products.- 3 years of experience leading packaging NPI activities for Analog Devices’ MEMS and RF SiP products.- 7 years of experience leading packaging NPI activities for Qualcomm’s industry-leading cellular modem products, and continuously driving these products to thinner/smaller packages, by closely managing top assembly houses in planning and execution of Package Characterization and Qualification activities.- Extensive knowledge in electronic packaging processes including wafer bumping, die prep, flip chip attach, plasma, wire bond, molding, ball attach, SMT, and packaging materials including molding compound, underfill, flux and solder paste, conductive/non-conductive die attach material, and dam & fill encapsulant.
Listed skills include Electronics Packaging, Design For Six Sigma Black Belt, Lean Sigma Green Belt, Doe, and 19 others.
Lejun Wang's current company
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Lejun Wang work experience
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Semiconductor Packaging Engineer
Led packaging NPI activities for Analog Devices’ MEMS Gyroscope and Accelerometer and RF SiP products.
Sr. Staff Engineer
Led packaging NPI activities for Qualcomm’s industry-leading cellular modem products to ensure new products meet assembly yield (> 99.5%) and reliability targets.Driven package technology development that enables modem product roadmap going thinner/smaller generation after generation, with package thickness reduced by 46% and size by 36%.Led or participated in cross functional teams to resolve a number of yield or reliability issues encountered during package NPI.
Sr. Principal Packaging Engineer
Led a cross-functional team to successfully resolve assembly issues of an asymmetric surface mountable transformer in SMT process under tight schedule - Utilized tools that include Surface Evolver, finite element analysis, and digital image correlation to quickly identify root cause and determine solution paths. - Improved assembly yield of the transformer from 85% to 99.6% in six months, which prevented major schedule delay to the qualification of the new defibrillator product, and led to ~$10M in saving annually for scrap reduction.Recognized as a subject matter expert in polymer materials and molding technologies at Medtronic Tempe Campus; consulted on these subjects by multiple projects
Principal Process Engineer
Led development activities to replace legacy chip and wire assembly line with new high power lean line to achieve size reduction, cost reduction, and reliability improvement. - Developed new processes that include transfer molding and ion free plasma, down-selected new material sets that include epoxy molding compounds, conductive and non-conductive die attach adhesives for better MSL performance (from 5 to 2A) and lower cost. - Led multi-functional working groups to identify root cause and implement fix for major yield and reliability issues that include die attach delamination, die cracking, component leakage instability, and incomplete fill in molding.Led development activities to establish transfer molding process and select epoxy molding compounds for stack-die CSP and HV SiP electronic modules. - Established transfer molding process, selected low stress low alpha epoxy molding compound for internal stack-die CSP prototyping to demonstrate functionality and robustness of first silicon and new package designs. - Established transfer molding process, selected high performance epoxy molding compound, and established substrate design rules for development of HV SiP electronic modules. Led development activities to reduce hybrid encapsulant height to enable volume and thickness reduction on next generation electronic module for defibrillators - Achieved 20% encapsulant height reduction on dam & fill process which led to 10% longevity improvement. - Achieved 10% yield improvement and 33% UPH improvement on dam & fill process by replacing LCP dam with Integral Dam Stiffener and Auger pump with Multi-piston pump.
Senior Engineer
Led underfill process development for packaging Intel’s next generation CPU, chip set, and network processor products.- Developed a high yield underfill process that is High Volume Manufacturing friendly and with 40% of UPH improvement over previous generation process.- Managed smooth technology transfer to multiple Virtual Factory sites by ensuring Copy Exactly.- Qualified underfill for Intel’s next generation products that meets manufacturability, reliability (lead and lead-free), and cost requirements.Led working group activities to achieve balance between underfill processability and electrical performance.- Validated package epoxy exclusion zone across all form factors of Intel’s next generation products.- Forced re-design of two high volume products by intercepting at early design stage to avoid assembly yield caused by Design for Manufacturability issue.- Identified design and process solutions to reduce epoxy exclusion zone; Adopted design solutions into substrate Design Rule
Lejun Wang education
Ph.D., Materials Science & Engineering
Ms, Polymer Engineering
Ms, Polymer Chemistry
Bs, Chemistry
Frequently asked questions about Lejun Wang
Quick answers generated from the profile data available on this page.
What company does Lejun Wang work for?
Lejun Wang works for Allegro MicroSystems.
What is Lejun Wang's role at Allegro MicroSystems?
Lejun Wang is listed as Packaging Engineer at Allegro MicroSystems at Allegro MicroSystems.
What is Lejun Wang's email address?
AeroLeads has found 1 work email signal at @analog.com for Lejun Wang at Allegro MicroSystems.
Where is Lejun Wang based?
Lejun Wang is based in Wilmington, Massachusetts, United States while working with Allegro MicroSystems.
What companies has Lejun Wang worked for?
Lejun Wang has worked for Allegro Microsystems, Analog Devices, Qualcomm, Medtronic, and Intel Corporation.
How can I contact Lejun Wang?
You can use AeroLeads to view verified contact signals for Lejun Wang at Allegro MicroSystems, including work email, phone, and LinkedIn data when available.
What schools did Lejun Wang attend?
Lejun Wang holds Ph.D., Materials Science & Engineering from Georgia Institute Of Technology.
What skills is Lejun Wang known for?
Lejun Wang is listed with skills including Electronics Packaging, Design For Six Sigma Black Belt, Lean Sigma Green Belt, Doe, Spc, Fmea, Csp, and Characterization.
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