A Chartered Engineer and manager with 26 years experience across the ASIC, FPGA and software design cycle from requirements capture, through to GDSII tape out and software release. A broad and comprehensive technical knowledge is complimented by good interpersonal skills, teamworking and project planning.Specialities: System architecture design; Hardware / software partitioning; ASIC / FPGA (System)Verilog RTL implementation; constrained random coverage driven verification (CDV). Optimising architectures and designs for: test; verification; synthesis; floorplan; place and route; power; STA. Autogeneration tools, infrastructure design and implementation. Software algorithms, ISO26262. Lab and in field bringup and validation.Managing all the above.Technical domains: Autonomous Vehicles, FFT, DSP, radar processing, image processing and analysis, SIMD processor design.
Listed skills include Asic, Rtl Design, Fpga, Functional Verification, and 38 others.