Lewis Sternberg Email & Phone Number

Arlington, VA, US

FPGA Design Verification

Charlotte, North Carolina, US

FPGA design verification

Santa Clara, California, US

• Architect./build testbenches in UVM. Cluster Level Testbench for MBY (Ethernet Switch) Rx_PPE. Unit Level Testbench for DHV (Optane Memory Controller) Security Unit
• Post-processing code in Python for CPU emulation (Zebu), synthesizable code for End of Test.
• Contributor: OPA (Networking Group) Verification Methodology Working Group
• Implement testbench support for a set of Reliability-And-Security features in CWV (Optane Controller)
• DHV Security FIPS verification

• Create AXI behavioral memory model. Cut simulation time by 66%

Arlington, VA, US

• Architect the HW/SW interface and common blocks for 3 FPGAs for maximum design reuse & verification
• Write DV verification plans from scratch
• Architect UVM testbench for said 3 FPGAs

• OmniPath Gen 2 – Software Defined Networking
• On-Chip Processor interface and Full-chip validation with SystemVerilog / OVM

• Review and interpret technical evidence on a high-profile case

Centennial, Colorado, US

• Validation of sRIO (Rapid IO) and SpaceWire interfaces and associated performance and error registers for space-bound memory subsystem DMA chips in a SystemVerilog / UVM environment.

Santa Clara, California, US

• Full-chip pre-silicon validation of Lewisburg Platform Control Hub (PCH) using SystemVerilog and OVM
• Focus on verifying Gigabit Ethernet MAC 10/100/1000T at the full-chip level

Carlsbad, CA, US

• Architect cluster-level testbench for RX PHY and MAC of a 60GHz low-power WiGIG ASIC project using C and SystemVerilog

Santa Clara, California, US

• Architect cluster-level testbench within CPU core of Xeon Phi / MIC (Many Integrated Core) project using eUVM and Specman
• C++ / SystemVerilog unit-level testbench

US

• Develop unit-level testbench for STL256 interface for a 300M-gate, 120Gbps networking chip using Specman and eUVM

Santa Clara, California, US

• Develop tests for QPI-based hardware accelerator platform (QuickAssist)
• Modify OVM verification components and scripts as needed

Hillsboro, OR, US

• Design RTL block for DDR3 read-reorder block.
• PCI-Express Phy integration
• Verilog-to-VHDL translation of PCI-Express 3 design blocks

San Jose, California, US

• Developed cycle-accurate SystemC Models

San Jose, CA, US

• Create VerilogAMS models of analog baseband path and power-control blocks for full-chip functional verification.

Arlington, VA, US

• Full chip integration and debug of RTL and Specman testbench for a rad-hard 49-processor IC including 10 GB Ethernet (XAUI) and XGMII interfaces.

San Jose, CA, US

• Architect and code coverage for a VMM SystemVerilog testbench of an SOC performing low-latency H/W scanning of 10GB Ethernet traffic.

Wilsonville, OR, US

• Conversion of legacy testbench to SystemVerilog for a set-top-box SOC for a client of Mentor Graphics’ Design Services organization using Questa, AVM

Santa Clara, California, US

• Architect Multi-Cluster Testbench for Larrabee (advanced graphics) project using Specman Elite
• Architect and execute PCI-Express switch testbench

Norwalk, Connecticut, US

• Develop Requirements, Specification, and Test Plan for a low-cost high-speed serial bus for an industrial environment
• Execute lab tests and document results

Dallas, TX, US

• Architected module-level testbench using Specman.

Santa Clara, California, US

• Create testbench for PCI-Express-like bus & RMII bus using eRM.
• Modify legacy Specman Elite testbench for reuse with a Gigabit Ethernet MAC 10/100/1000T
• Verified critical initialization sequences and CSRs
• 1st silicon fully fuctional

US

• Verified SOC core-bus optimization using Verilog and Specman Elite
• Verified critical initialization sequences
• Optimized internal tools for use with NC-Sim, Specman Elite, Simvision and Debussy

Poway, California, US

• Developed Analog Mixed-Signal Verification Plan for 4GHz serdes full-custom IC.
• Wrote Verilog-AMS measurement modules and testbenches for critical-path analyses.
• Developed and documented core digital algorithm for serdes training sequence.

• Brought up and verified circuit board with high-speed Altera FPGAs and CPLDs.
• Wrote Verilog code, simulated with ModelSim and synthesized in Mentor Graphics’ Leonardo for board production self-test.
• Documented board test usage and procedures.

US

• Taught 3-day Specman Basic Training Course at Verisity’s headquarters and Fortune 500 customer sites.

Armonk, New York, NY, US

• Verified 300,000 gate block in a multi-million gate cache coherency ASIC for an IA-64 based multi-processor system using Specman Elite, e, Verilog, and VHDL to ensure 1st silicon success.
• Developed solutions to test inter-partition messaging – bringing new functionality to the NUMA-Q product line.
• Created methodology to carry verification techniques into laboratory testing saving considerable time and eliminating duplicate efforts.

• Designed behavioral models to allow IP integration in an ADSL line card ASIC using Verilog, e, Specman Elite.
• Developed tests for a terabit router to ensure architecture’s scalability (tcl, VHDL).
• Opened new markets to Qualis by expanding verification IP to include Analog-Mixed-Signal (VHDL-AMS).
• Trained hundreds of engineers on high-level verification methodologies using VHDL, Verilog.
• Delivered papers to leading technical conferences to increase Qualis’ presence and stature.

• Made Analog-Mixed-Signal virtual test a reality by creating simulation models of ICs and testers.
• Created library products for development of DUT models in a variety of languages: SpectreHDL, MAST, Verilog, Verilog PLI, Skill, SPICE with Cadence’s Artist.
• Modeled testers for use in Dantes virtual test product: Teradyne, Credence, and LTX.

• Consultant, 1994, 1997
• Created tactical and strategic competitive analysis of Analogy and Cadence products for a comprehensive in-depth presentation to the annual Analogy global sales meeting.
• Developed and delivered Analogy’s feature presentation at the Design Automation Conference. Senior Design Engineer, 1986 – 1994
• Facilitated growth of Portland Center from a start-up of 10, without a customer to a growing international company of 135 with a diversified customer base including the leaders of the aerospace, automotive, power.
• Conceived, created, and brought to market a library of advanced test and measurement models.
• Founded Consulting Department, created the business plan, marketing collateral, and handled all quotes and statements of work, grossing over $110,000 in my first year.