Lewis Sternberg's Location
Portland, Oregon, United States, United States
Lewis Sternberg's Contact Details
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About Lewis Sternberg
Senior-level verification engineer. Motivated top performer with excellent training, communication and interpersonal skills. A proven track record in identifying problems and developing innovative solutions. Paper on AMS Verification on-line at:http://www.star-mountain.com/AMS_Verification.pdfProven: Almost all my work since 2000 has been repeat business with colleagues and managers I’ve worked with before.I'm incorporated (Star Mountain, Inc.) and available corp-to-corp, 1099 and W-2.Specialties: Functional Verification, Training, SystemVerilog, Verilog-AMS, VHDL, VHDL-AMS, Saber, MAST, Specman, e, ASIC, VLSI, FPGA, Analog Mixed-Signal, methodology. eRM OVM, UVM.
Lewis Sternberg Work Experience Details
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Senior Design Verification EngineerBoeing 2024 - PresentArlington, Va, UsFPGA Design Verification -
Senior Design Verification EngineerCollins Aerospace 2024 - 2024Charlotte, North Carolina, UsFPGA design verification -
Senior Design Verification EngineerIntel Corporation 2018 - 2023Santa Clara, California, Us• Architect./build testbenches in UVM . Cluster Level Testbench for MBY (Ethernet Switch) Rx_PPE . Unit Level Testbench for DHV (Optane Memory Controller) Security Unit• Post-processing code in Python for CPU emulation (Zebu), synthesizable code for End of Test.• Contributor: OPA (Networking Group) Verification Methodology Working Group• Implement testbench support for a set of Reliability-And-Security features in CWV (Optane Controller)• DHV Security FIPS verification -
Senior Design Verification EngineerGenia Technologies 2018 - 2018• Create AXI behavioral memory model. Cut simulation time by 66%
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Senior Design Verification EngineerBoeing 2017 - 2018Arlington, Va, Us• Architect the HW/SW interface and common blocks for 3 FPGAs for maximum design reuse & verification• Write DV verification plans from scratch• Architect UVM testbench for said 3 FPGAs
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Senior Design Verification EngineerIntel 2016 - 2017• OmniPath Gen 2 – Software Defined Networking • On-Chip Processor interface and Full-chip validation with SystemVerilog / OVM
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ConsultantOffice Of The Federal Public Defender 2016 - 2016• Review and interpret technical evidence on a high-profile case
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Senior Design Verification EngineerSeakr Engineering 2015 - 2015Centennial, Colorado, Us• Validation of sRIO (Rapid IO) and SpaceWire interfaces and associated performance and error registers for space-bound memory subsystem DMA chips in a SystemVerilog / UVM environment. -
Senior Design Verification EngineerIntel Corporation 2014 - 2015Santa Clara, California, Us• Full-chip pre-silicon validation of Lewisburg Platform Control Hub (PCH) using SystemVerilog and OVM• Focus on verifying Gigabit Ethernet MAC 10/100/1000T at the full-chip level
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ConsultantTensorcom 2014 - 2014Carlsbad, Ca, Us• Architect cluster-level testbench for RX PHY and MAC of a 60GHz low-power WiGIG ASIC project using C and SystemVerilog -
Senior Design Verification EngineerIntel 2012 - 2013Santa Clara, California, Us• Architect cluster-level testbench within CPU core of Xeon Phi / MIC (Many Integrated Core) project using eUVM and Specman• C++ / SystemVerilog unit-level testbench
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Senior Design Verification EngineerPmc-Sierra 2011 - 2012Us• Develop unit-level testbench for STL256 interface for a 300M-gate, 120Gbps networking chip using Specman and eUVM -
Senior Design Verification EngineerIntel 2011 - 2011Santa Clara, California, Us• Develop tests for QPI-based hardware accelerator platform (QuickAssist) • Modify OVM verification components and scripts as needed
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Senior Design Verification EngineerNorthwest Logic 2010 - 2010Hillsboro, Or, Us• Design RTL block for DDR3 read-reorder block.• PCI-Express Phy integration• Verilog-to-VHDL translation of PCI-Express 3 design blocks -
Senior Design Verification EngineerMips Technologies 2009 - 2010San Jose, California, Us• Developed cycle-accurate SystemC Models -
Senior Design Verification EngineerIntelleflex 2009 - 2009San Jose, Ca, Us• Create VerilogAMS models of analog baseband path and power-control blocks for full-chip functional verification. -
Senior Design Verification EngineerBoeing 2008 - 2008Arlington, Va, Us• Full chip integration and debug of RTL and Specman testbench for a rad-hard 49-processor IC including 10 GB Ethernet (XAUI) and XGMII interfaces.
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Senior Design Verification EngineerLsi 2008 - 2008San Jose, Ca, Us• Architect and code coverage for a VMM SystemVerilog testbench of an SOC performing low-latency H/W scanning of 10GB Ethernet traffic. -
Senior Design Verification EngineerMentor Graphics 2007 - 2007Wilsonville, Or, Us• Conversion of legacy testbench to SystemVerilog for a set-top-box SOC for a client of Mentor Graphics’ Design Services organization using Questa, AVM -
Senior Design Verification EngineerIntel 2006 - 2007Santa Clara, California, Us• Architect Multi-Cluster Testbench for Larrabee (advanced graphics) project using Specman Elite• Architect and execute PCI-Express switch testbench
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Senior Design Verification EngineerXerox 2006 - 2006Norwalk, Connecticut, Us• Develop Requirements, Specification, and Test Plan for a low-cost high-speed serial bus for an industrial environment• Execute lab tests and document results -
Senior Design Verification EngineerTexas Instruments 2006 - 2006Dallas, Tx, Us• Architected module-level testbench using Specman. -
Senior Design Verification EngineerIntel 2004 - 2005Santa Clara, California, Us• Create testbench for PCI-Express-like bus & RMII bus using eRM.• Modify legacy Specman Elite testbench for reuse with a Gigabit Ethernet MAC 10/100/1000T• Verified critical initialization sequences and CSRs• 1st silicon fully fuctional
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Senior Design Verification EngineerPmc-Sierra 2003 - 2004Us• Verified SOC core-bus optimization using Verilog and Specman Elite• Verified critical initialization sequences• Optimized internal tools for use with NC-Sim, Specman Elite, Simvision and Debussy
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Senior Design Verification EngineerCredence 2003 - 2003Poway, California, Us• Developed Analog Mixed-Signal Verification Plan for 4GHz serdes full-custom IC.• Wrote Verilog-AMS measurement modules and testbenches for critical-path analyses.• Developed and documented core digital algorithm for serdes training sequence. -
Senior Design Verification EngineerTeseda 2002 - 2003• Brought up and verified circuit board with high-speed Altera FPGAs and CPLDs.• Wrote Verilog code, simulated with ModelSim and synthesized in Mentor Graphics’ Leonardo for board production self-test.• Documented board test usage and procedures.
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Design Verification EducatorVerisity 2001 - 2002Us• Taught 3-day Specman Basic Training Course at Verisity’s headquarters and Fortune 500 customer sites. -
Senior Design Verification EngineerIbm 2001 - 2002Armonk, New York, Ny, Us• Verified 300,000 gate block in a multi-million gate cache coherency ASIC for an IA-64 based multi-processor system using Specman Elite, e, Verilog, and VHDL to ensure 1st silicon success.• Developed solutions to test inter-partition messaging – bringing new functionality to the NUMA-Q product line.• Created methodology to carry verification techniques into laboratory testing saving considerable time and eliminating duplicate efforts. -
Senior Design Verification EngineerQualis 1999 - 2001• Designed behavioral models to allow IP integration in an ADSL line card ASIC using Verilog, e, Specman Elite.• Developed tests for a terabit router to ensure architecture’s scalability (tcl, VHDL).• Opened new markets to Qualis by expanding verification IP to include Analog-Mixed-Signal (VHDL-AMS).• Trained hundreds of engineers on high-level verification methodologies using VHDL, Verilog.• Delivered papers to leading technical conferences to increase Qualis’ presence and stature.
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Senior Ams Modeling EngineerIms 1995 - 1999• Made Analog-Mixed-Signal virtual test a reality by creating simulation models of ICs and testers.• Created library products for development of DUT models in a variety of languages: SpectreHDL, MAST, Verilog, Verilog PLI, Skill, SPICE with Cadence’s Artist.• Modeled testers for use in Dantes virtual test product: Teradyne, Credence, and LTX.
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Senior Design EngineerAnalogy 1986 - 1997Consultant, 1994, 1997• Created tactical and strategic competitive analysis of Analogy and Cadence products for a comprehensive in-depth presentation to the annual Analogy global sales meeting.• Developed and delivered Analogy’s feature presentation at the Design Automation Conference. Senior Design Engineer, 1986 – 1994• Facilitated growth of Portland Center from a start-up of 10, without a customer to a growing international company of 135 with a diversified customer base including the leaders of the aerospace, automotive, power conversion and medical industries. • Conceived, created, and brought to market a library of advanced test and measurement models. • Founded Consulting Department, created the business plan, marketing collateral, and handled all quotes and statements of work, grossing over $110,000 in my first year.• Founded the Customer Support and Training Department.• Designed, wrote, maintained and delivered training classes to over 1,000 engineers.
Lewis Sternberg Skills
Verilog
Asic
Systemverilog
Functional Verification
Soc
Debugging
Fpga
Eda
Vhdl
Vlsi
Modelsim
Processors
Ic
Application Specific Integrated Circuits
Tcl
Simulations
Logic Design
Specman
Uvm
Hardware Architecture
Pcie
System On A Chip
Field Programmable Gate Arrays
Cadence
Spice
Very Large Scale Integration
Mixed Signal
Integrated Circuits
Ncsim
Systemc
Vhdl Ams
Serdes
Analog
Open Verification Methodology
Vmm
Simulation
Lewis Sternberg Education Details
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Oregon State UniversityBsee
Frequently Asked Questions about Lewis Sternberg
What company does Lewis Sternberg work for?
Lewis Sternberg works for Boeing
What is Lewis Sternberg's role at the current company?
Lewis Sternberg's current role is Senior Design Verification Engineer.
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What schools did Lewis Sternberg attend?
Lewis Sternberg attended Oregon State University.
What are some of Lewis Sternberg's interests?
Lewis Sternberg has interest in Education.
What skills is Lewis Sternberg known for?
Lewis Sternberg has skills like Verilog, Asic, Systemverilog, Functional Verification, Soc, Debugging, Fpga, Eda, Vhdl, Vlsi, Modelsim, Processors.
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