- Understood the simulation flow of block-level UVM environment which uses CSIM as a reference model.- Created block-level test plans by investigating the impact of a new feature from Microarchitecture Specification- Implemented testbench changes based on the reviewed test plan.- Implemented C-model/CSIM changes for verification of design features.- Continuously debug issues for CSIM, RTL and testbench by utilizing tools such as Synopsys Verdi and GNU Debugger to root cause existing errors and provide fixes to help the team achieve and maintain a high regressionsuccess rate.- Familiarized with TDL test flow and migrated the complete test suite from DV test flow to TDL test flow for the GFXIP sub-system block.- Familiarized with version control tool Perforce and managed integrations across different code lines.