Senior Member Of Consulting Staff
San Jose, California, Us
C/C++, Perl, TCP/IP. Compiler, Synthesis, Parallel Computing. Performance OptimizationFor emulators using arrays of FPGA (Field-Programmable Gate Array) or custom Microprocessors, the challenge of the software compiler is to achieve orders of magnitude speedup than software simulators, while providing debugging abilities.__Technical Leadership__• Outstanding ability to independently understand the complex source code base, evolved from generations of software releases through multiple companies• Contributed to various areas of the hardware compiler spanning: parsing Hardware Description Languages, scheduling, code generation, clustering/partitioning into chips, memory mapping, mapping to ALUs, distributed processing for multiple PCs/cores, encryption for IP, and interface with debugging tools• Expertise in runtime, data structure and memory optimization and compile flow improvement• Expertise in comprehending complex algorithms and data structures in legacy code through tracing and analysis__Project Leadership__• Led the specification and implementation of workflow, complex features, unit and integration test plans in several software releases• Supported field engineers of major clients, for complex customer applications with mixed hardware description languages, and varied tool environments• Led the definition and delivery of new features by negotiating and collaborating with cross-functional teams: backend compiler, hardware architect and field engineers• Resolved several integration issues, involving APIs, embedded assertion features, data formats, memory downloads and GUI interfaces, by applying technical knowledge, while demonstrating leadership and communication skills• Developed several advanced features, that normal synthesis tools cannot support: configuration and mixed language support