Lim Jun Shen is a Formal Verification Engineer at AMD. Colleagues describe them as "I worked alongside Lim as the design engineer for units he was verifying, and from the off he did a great job, he understood the design quickly, asked all the right questions, and delivered on everything. Definitely one to watch in the future with great potential!" and "Worked with Jun Shen on multiple digital circuit designs, he is able to identify and improve upon existing state machine designs. He always strikes a great impression on me with his passion and attention to detail in programming System Verilog and C for digital circuit systems."