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Lino Li is a Semiconductors Professional at Qualcomm. He possess expertise in rtl design, modeling, synopsys primetime, logic synthesis, cadence virtuoso and 11 more skills.
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Principal EngineerQualcomm Jul 2013 - PresentSan Diego, Ca, Us -
Mts Asic EngineerAmd 2004 - 2012Santa Clara, California, Us• Designed Digital logics for Multiple IO interfaces; Focused on IP reuse and Boundary Scan support• Owned Ontario DDRPHY; Coordinated multiple teams for design specs, schedule and resources• Implemented PLL / DLL Logic blocks. Handled multiple clock domains with custom timing check• Developed and delivered 65nm MIPI D-PHY• Created and verified behavior models for Analog IPs • Implemented Memory PAD interface logics, including RTL design, synthesis, Place & Route, STA Timing signoff and Mixed signal simulation• Developed perl script to customize DDRPHY clock tree • Investigated Signal Integrate Issue for RS600 chipset.• AMD/ATI Chipset Memory interface Bringup• IP validation, including characterization / ADM verification / LVS / DRC etc• Constructed IBIS models for IO PADs.• IO ring integration• Full Custom Layout of IO PAD
Lino Li Skills
Frequently Asked Questions about Lino Li
What company does Lino Li work for?
Lino Li works for Qualcomm
What is Lino Li's role at the current company?
Lino Li's current role is Semiconductors Professional.
What is Lino Li's email address?
Lino Li's email address is li****@****omm.com
What skills is Lino Li known for?
Lino Li has skills like Rtl Design, Modeling, Synopsys Primetime, Logic Synthesis, Cadence Virtuoso, First Encounter, Perl, Tcl Tk, Dft, Boundary Scan, Ddr3, Mipi.
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