Technical Expertise:  Architecting complete RTL to GDSII flow including Synthesis, Physical Design, Constraints and STA. 15Years of industry experience and worked in technologies ranging from 65nm to 4nm. Lead complete SoC implementation including planning, partitioning, allocating resources, scheduling. Worked as Timing expert and lead the complete SoC and IP level constraints development and signoff. Hands on Experience on EDA-Tools like Design Compiler, ICC/ICC2 , PrimeTime, Spyglass, Formality. Well verse with languages like Perl, TCL.