Luc Engrand Email & Phone Number

Nice, Fr

Nice, Provence-Alpes-Côte D'Azur, France

In charge of Business Development of CEVA IPs (HW and SW) and Design Services solutions for South and Central Europe

Région De Nice, France

In charge of growing sales revenue of e-peas in EMEA region through Direct Customers and by managing the different Sales Channels (distributors, reps). Main market segments are Industrial 4.0, Wearables, Healthcare, Automotive, IoT.

Sophia-Antipolis

Responsible for growing revenue of Insight SiP with Design Service solutions to addresscustomer system in package requirements. Focus on Business Development in Europe, North America and Asia regions.

Nice Area, France

Nice Area, France

Nice Area, France

Corbeil-Essonnes (Paris, France)

In charge of developing Altis Semiconductor open foundry solutions to address specific market segments like Automotive, eSecurity, Telecom, Industrial.This involves close cooperation with R&D (for technology roadmap definitions), Design Center (to enable complete ecosystem, like IPs, EDA alliances and Reference Flows) and existing/future customers

Paris Area, France

Amsterdan

Working from TSMC European Headquarter in Amsterdam.Deputy of the Field Technical Support (FTS) Director, in charge of:- providing pre tape-out support to european customers with local FAE team- defining potential business opportunities and forecast tapouts

Amsterdam Area, Netherlands

Program Manager of ASIC digital basebands for the wireless handset industry, coordinating R&D activities, with close relationship with manufacturing sites

Nice Area, France

Team Leader of the ASIC Field Applications Engineer Group in the European Wireless Business Unit. This function aimed to provide design support to the same major Northern European Customer. This involved on-site support, CAD flows and methodologies, ASIC design techniques and DFTs, technology integration (gate-array, standard-cells), design quality check, trainings. Target devices were a range of cDSP chips for mobile phones integrating TI DSPs (LEAD/C54X), a 32-bit RISC Microprocessor (ARM series) on an ASIC back-plane (TI 0.25/0.18/0.15um Std-Cell technologies). This position implied close relationship with the different TI departments such as MCU, DSP and ASIC.Those responsabilities allowed me to strengthen my experience with VHDL, Mentor tools (Quicksim, QuickHDL/ModelSim, Fastscan), Synopsys combined with the TI ASIC flow on HP platforms.

As a Senior Design Engineer I was involved in several DTI research programs for Behavioural Synthesis of VLSI systems. Three complex digital ASICs were designed with experience gained in HDLs (ELLA, MODEL), Logic Simulator, Auto-placement/route and layout generations. In parallel I was also in charge of different full/semi-custom CMOS VLSI designs. I was also involved in the maintenance of the SMS Multisourceable Cell Libraries with the addition of VAX System Manager functions.

Msc, Microelectronics

Activities and Societies: The syllabus of the course covers digital and analog electronics with emphasis on the design of silicon.

Ingenieur, Electronics