Lucas Jo Email & Phone Number

South Korea

South Korea

Korea

Developing Virtual assistant based on ML tech.Project: Zerothhttps://github.com/goodatlas/zerothKaldi-based Korean ASR open-source projectBy introducing an official Korean Kaldi recipe, the Zeroth project aims to make Korean speech recognition more broadly accessible to everyone.Now Project:Zeroth Korean transcribed audio and LMs are available at http://www.openslr.org/40/

Jung-Gu, Seoul, Korea

building voice data verification and speaker recognition tools.

Pangyo, Korea

Ripplebuds ProjectNoise-blocking wireless Bluetooth earbuds with an in-ear microphone. Analyzed the sound quality degradation of the user's voice which is picked up in the ear. Discovered that the measured voice spectrum within the near-end user’s ear is broadly boosted 20 dB or more at 300~400 Hz and identified that this is the same phenomenon known as the occlusion effect. Proposed a time-varying multi-band equalizer with band-gain control by trained Neural Network and Confirmed that the speech signal was restored to a level substantially similar to the original speech by MATLAB airDAC ProjectHi-Fi DAC with Headphone Amplifier. Participated in development of airDAC: High End Wi-Fi / USB DAC. Explored existing ASIC solutions to design analog audio signal part consisting of DAC, I/V filter, PGA, and headphone amplifier that can meet high-end audio quality. Performs a power budget analysis to supports appropriate power to the system and allows targeted drivability on the headphone amplifierDescribed a high-level design document for ordering PCB outsourcing. Exhibited the products at the 2016 High-end Show in Munich. Contributed to good reviews from Mono and stereo. The review is posted at http://www.monoandstereo.com/2016/03/radsone-airdac-ad-200-review.html

Seoul, Korea

Class D Amplifier with Class H SMPSEfficiency improvement of Class D amplifier systemConceptualized two different schemes for digital audio PWM modulator to improve efficiency of Class-D amplifier output stage. PWM switching frequency shift (ex. 384 kHz → 192 kHz) to decrease switching loss at the output stage. PVDD level control according to input signal envelope variation to reduce heat loss due to maintaining high PVDD level. Implemented the switching frequency shift algorithm on playback without click noise by maintaining PWM continuity. Collaborated with H/W application engineer to design Class-H SMPS which takes external varying reference voltage. Achieved up to 40% efficiency improvement in Class-D amplifier at the listening level music signal.

Seoul, Korea

AATP (Audio Algorithm Test Platform)Real-time Audio Algorithm Verification Tool Developed Windows Winamp plugin to evaluate audio algorithms in real-time in developing phase (Coded the plug-in with QT 4.x and C/C++). Implemented existing sound processing algorithms in C: parametric EQ, QXpander, virtual bass, dynamic range compressor and etc.Implemented real-time analysis tools: waveform, spectrogram and FFT. Reduced time spent on algorithm verification in the development process.PS8645One chip solution PS8645 with USB input audio + PWM modulator + 5W Class-D amplifierAdopted by SONY for iPhone docking speaker product. Worked as ASIC front-end engineer along with a team of 7 members. Merged newly upgraded PWM modulator (mentioned below) into the system. Implemented sound processing algorithms: parametric EQ, virtual bass enhancement, QXpander, DRC. Co-worked successfully with firmware and hardware application engineers. Collaborated on making firmware drivers to control PWM modulator and sound processing blocks on FPGA environment (virtex 5) New PWM EnginePerformance Improvement of Digital Audio PWM ModulatorBuilt MATLAB simulation for performance evaluation of PWM modulator system. Analyzed with the simulation on the blocks such as asynchronous sample-rate converter, oversampler, digital delta-sigma noise shaper, PCM to PWM converter to identify optimization points on the existing system. Designed a pre-distortion block of noise-shaper to improve modulation linearity like naturally-sampled PWM in analog PWM modulation (implemented on FPGA virtex 5). Improved THD(Total Harmonic Distortion) 20 dB or more at the end of the amplifier outputUpgrade performance of asynchronous sample-rate converter with external jittered input.Designed a digital PLL to reduce external jitter and predict accurate resampling point to increase ASRC output signal-to-noise ratio (SNR) to more than 115dB

Seoul, Korea

Optimized network parameters with a team of 9 members to extend EVDO rev.A wireless network coverage and throughputDocumented optimization process to train local operations center staffs