Leading a team to develop a very complex random test case generator for company's RISC-V designs.

Develop tools, flows and methodologies for core verification, simulation, performance analysis, etc, with Python/Shell scripts and in-house/vendor verification tools. Develop random test case generator for software-driven RTL verification. Design and develop post-processing hardware-software co-debug tool. ARM/PowerPC/RISC-V processor architecture modeling and instruction set simulator development.

Static Timing Analysis (STA) and critical path improvement---- Wrote tcl script to control automated simulation/synthesis process---- Used two-level for-loop to replace case structure to improve critical path---- Clock enable tree improvement to reduce clock enable fan-outPrefetch cache architecture design and implementation in VHDL---- Adaptive set associative according to given data pattern---- Analyzed given data pattern to prefetch data to speed up SRAM read/write

MIPS 5-stage pipeline architecture simulator implementation and optimization in C++---- Optimized branch prediction with a parallel branch fetching architecture---- Tested with multiple instruction set including multi-cycle multiplying and dividingMicroprocessor multi-task scheduling algorithm design and implementation in C++---- Simulated Annealing algorithm implemented and adjusted with specific parameters of different task properties---- Journal paper published on IEEE Embedded System LettersMemory-efficient Finite-State-Machine architecture design in VHDL---- Designed two RTL level FSM architecture implementations (2-RAM; 3-RAM)---- Wrote Perl script to help testing automation; Conference paper published on ASAP 2013Storage-efficient FFT butterfly architecture design and implementation---- Designed a delay-cross-delay pattern architecture that required no data storage between each two stages---- layout generated in CADENCE; passed LVS and DRCN-body simulator implementation---- Implemented Barns-Hut algorithm in MPI, UPC and SHMEM separately---- Implemented and tested the performance of parallelized N-body simulator on 2, 4, and 8 nodes separatelyParallelized image processing architecture emulation on Altera Stratix III FPGAs---- Designed a RTL level 4-FPGA parallelized version of application utilizing parallel-beam filtered backprojection algorithm---- System architecture designed in Quartus II; Emulation platform: GiDEL ProcStar IIIEthernet chat software development in C---- Utilizing TCP/IP and UDP protocols separately---- Users are able to conduct chat between server and client machines

Xilinx FPGA fast place & routing research tool integration in LabVIEW---- Integrated a fast PAR tool in LabVIEW FPGA to directly convert .vi file to final VHDL---- Created functionality of generating XML file from LabVIEW user design utilizing Visual C++

EEL 4712 Digital Design; EEL 4930/5934 Reconfigurable Computing---- Led labs, graded exams and final projects; utilizing Xilinx synthesis, partitioning and routing tools---- Utilizing Verilog/VHDL---- EEL 4930/5934 Emulation Platform: Nallatech board