Luis G. Murillo

Luis G. Murillo Email and Phone Number

Director SW Engineering - AI Tools & Compilers @ AMD @ AMD
Sunnyvale, California
Luis G. Murillo's Location
Cologne, North Rhine-Westphalia, Germany, Germany
About Luis G. Murillo

Luis G. Murillo is a Director SW Engineering - AI Tools & Compilers @ AMD at AMD. They is proficient in German and English.

Luis G. Murillo's Current Company Details
AMD

Amd

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Director SW Engineering - AI Tools & Compilers @ AMD
Sunnyvale, California
Website:
amd.com
Luis G. Murillo Work Experience Details
  • Amd
    Director Sw Development - Ai Tools And Compilers
    Amd Feb 2022 - Present
    Santa Clara, California, Us
    Building and leading a world-class team of AI/ML tools and compiler engineers to build next-gen AI acceleration solutions.
  • Xilinx
    Ai/Ml Compilation Tools - Lead Cologne Site
    Xilinx Jun 2021 - Feb 2022
    San Jose, Ca, Us
  • Silexica
    Chief Technology Officer
    Silexica Apr 2020 - Jun 2021
    Cologne, De
    I manage the company’s technology strategy and assess new approaches and solutions for democratizing accelerated computing and mastering the software/hardware complexity at the intelligent edge and cloud.
  • Silexica
    Vice President Of Engineering
    Silexica Oct 2016 - Mar 2020
    Cologne, De
    I was part of the Executive team, reporting to the CEO. My main task consisted on building from scratch and leading the core software development teams behind the award-winning SLX Tool Suite, by transforming a handful of SW engineers into an over-performing, execution-driven department throughout our series A and B growth phases. Among others, I introduced agile methods for the development teams and supported the implementation of all related processes and roles along with the inception of CI, QA, DevOps, and release management processes, tools and roles. Within the Engineering team, I also managed the FAEs, AEs and consequently acted as the highest level decision making authority at the interface among the Sales, Engineering and Product teams. At earlier times I also did some product management/ownership as well as technical leadership for some key strategic customer engagements, early definitions of our core IP and product architecture and technology investigations to support the company strategy and product vision.
  • Silexica
    Engineering Manager
    Silexica May 2016 - Oct 2016
    Cologne, De
    R&D project management, solution management and management of strategic collaborations to broaden our technology and product portfolio.
  • Silexica
    R&D Engineer
    Silexica Jul 2015 - Apr 2016
    Cologne, De
  • Rwth Aachen University
    Research Staff, Institute For Communication Technologies And Embedded Systems
    Rwth Aachen University Oct 2009 - Oct 2015
    Aachen, North Rhine-Westphalia, De
    Researcher in HW/SW systems design and programming, specially targeting parallel programming, system-level analysis/optimization, SoC design, ESL simulation & virtual prototyping, HW/SW codesign, debugging and verification.
  • Euretile (European Commission Funded Project)
    Team Leader, Soc Simulation & Tool-Chain
    Euretile (European Commission Funded Project) Jan 2010 - Sep 2014
    Leader of the SoC simulation and tool-chain team. We developed processor instruction-set simulators, SoC models, compilers and debuggers for the massively parallel EURETILE architecture (EUropean REference TIled architecture EXperiment).
  • Advanced Learning And Research Institute, Alari
    Graduate Student Researcher
    Advanced Learning And Research Institute, Alari Sep 2007 - Sep 2009
    Ch
    Research assistant in multiple ALaRI projects from 2007 to 2009, mostly involving HW/SW design and development functions. An important part of my work was in the context of the AlpEnergy project (http://www.alpenergy.net/).
  • Noolah
    Algorithm Developer And Programmer
    Noolah 2008 - 2009
    Part of the development team creating data analysis algorithms for WSNs, using C++, Java, Python and (early)cloud technologies.
  • Universidad De Antioquia
    Research Assistant - Microelectronics Institute
    Universidad De Antioquia Oct 2006 - Sep 2007
    Medellín, Medellín, Co
    Design and development of digital signal processing hardware IP for live video and audio encoding, FPGA prototyping, processor interfacing and PCB design.
  • Interconexión Electrica S.A.
    Hardware Engineer
    Interconexión Electrica S.A. Jan 2006 - Sep 2006
    Medellín, Antioquia, Co
    Design, programming, set-up and maintenance of monitoring, automation and protection equipment for the Colombian electrical transmission network. This work included both software and hardware implementations on FPGAs for data acquisition and digital signal processing applications, in particular for measuring harmonic distortion

Luis G. Murillo Education Details

  • Rwth Aachen University
    Rwth Aachen University
    Electrical Engineering And Information Technology
  • Usi Università Della Svizzera Italiana
    Usi Università Della Svizzera Italiana
    Embedded Systems Design
  • Universidad De Antioquia
    Universidad De Antioquia
    Electronics

Frequently Asked Questions about Luis G. Murillo

What company does Luis G. Murillo work for?

Luis G. Murillo works for Amd

What is Luis G. Murillo's role at the current company?

Luis G. Murillo's current role is Director SW Engineering - AI Tools & Compilers @ AMD.

What schools did Luis G. Murillo attend?

Luis G. Murillo attended Rwth Aachen University, Usi Università Della Svizzera Italiana, Universidad De Antioquia.

Who are Luis G. Murillo's colleagues?

Luis G. Murillo's colleagues are Joanne Taylor, Srikanth Joshi, Jayashree Subramaniam, Ramesh Mantha, Jose Sunga, Dostonbek Mirzahamdamov, Gowtham G.

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