Luke Hood Email & Phone Number

Santa Clara, CA, US

Santa Clara, California, US

• Led the cross-site Hard Processor System (HPS) SOC RTL/logic design team for Intel's Programmable Solutions Group, formerly Altera, for inclusion into next-generation FPGA + SOC product.
• Worked with Architecture, Physical Design and Verification teams to understand challenges and drive efficient implementation solutions to meet product needs while easing convergence efforts.
• Collaborated with DA Teams from both Intel and Altera to converge on design environment solutions and drive methodology improvements.

Santa Clara, California, US

• Technical decision driver for architecture, microarchitecture and design development for high speed in-package memory implementation.
• Engineering Lead for feature scoping, resource planning and ramping cross-geo teams from path finding through tech readiness and execution. Received Division award for generational efficiency innovations.

Santa Clara, California, US

• SOC Project Logic Design Lead
• Led the planning, tracking and execution of logic design activities for an SOC design based in Penang, Malaysia.
• Coached and mentored a highly motivated team, while developing local cultural awareness and integrating the sensitivities and learnings into leadership techniques.IP Execution Lead for a cornerstone IP
• Drove technical development and execution of a brand new, cornerstone IP. Managed design risks and long poles to bring the IP design in on schedule and with budgeted resources.
• Developed technical expertise in low power design; honed skills in architecture/frequency/design library tradeoffs to meet customer landing zone requirements.

Santa Clara, California, US

• Planned, tracked and led logic design for an Intel SOC derivative project.
• Collaborated with architects and business unit to drive scope-controlled, quick turnaround, high value changes, fitting within SOC derivative design budget.
• Drove execution with customer focused philosophy, guiding logic design based on Validation and Structural design needs and milestones.

Santa Clara, California, US

• Audio Integration Lead for baseline Intel SOC design
• Led the Audio IP SOC integration and validation teams, working to plan, track and execute Audio integration for an Intel baseline SOC.
• Developed novel methods such as low-cost continuous SOC integration for coping with late IP delivery and variable quality IP, allowing structural design to stay on track for tape in.Owned microarchitecture and RTL.
• Leveraged significant past cache design experience to influence overall cache architecture definition. Owned microarchitecture definition and RTL development, executing to high level architecture spec.
• Completed RTL development on schedule and at high quality, significantly beating initial expectations. Collaborated with validation team to drive functional and performance validation strategies.

Santa Clara, California, US

• Logic design lead on Intel's second generation eDRAM design, integrated on package in the Intel Iris Pro 6200 product. Drove planning, tracking and execution of all logic development activities for the design.
• Owned tech-readiness activities, including quickly comprehending and exposing early design issues, identifying dependencies for all planned changes and producing an execution plan with predictable logic development and.
• Implemented tracking and reporting methodologies to quickly understand and react to unforeseen issues, keeping project execution on schedule.

Santa Clara, California, US

• Microarchitecture owner and RTL lead for Intel's first eDRAM controller, implemented in the Intel Iris Pro 5200 product. Collaborated with architects, designers and verification engineers to successfully execute.
• Coordinated back-end structural design planning, reconciling front-end and back-end milestones.
• Drove front end solutions to quickly react to backend issues such as timing convergence, congestion, clock and voltage crossing issues.

Santa Clara, California, US

• Intel 4th Generation Core (Haswell) Mid-level Cache Design Logic Lead
• Led cross-geo team responsible for logic design of the second level cache inside the core. Gained experience with managing design across geos and across cultures.
• Owned planning, tracking and execution of all logic design issues for a high performance cache, developing in-depth and instinctual level of understanding for cache related design issues such as timing convergence.
• Led APIC/xAPIC logic design over multiple Core generations.
• Led x2APIC Architecture Spec definition and logic development. Three patents granted.Intel Server Cache and Bus Interface Design
• Participated in microarchitecture and logic development for Intel's large cache versions of client microarchitectures, targeted for the server space.Intel Client Bus and APIC Validation

Ms, Computer Engineering

Bs, Electrical Engineering