Phoebe Luo Email & Phone Number

Toronto, On, Ca

Developed and updated UVM testbench for unit level verification for PCIe Gigabit Serializer-Deserializer PHY using COMPHY 56G 5nm design, tested functionalities including PCIe ECAM, FW loading, and CSR register R/W.

Developed Verilog module and testbenches for bus conversion and memory translation such as AXI, SRAM, Programmable IO specific instructions to ensure functionality and 100% test coverage. Performed FPGA testing to ensure the functionality of loaded new images, located and debugged the issue.

Developed SystemVerilog testbench to validate RTL block for Ethernet egress mirroring, implemented UVM component of interface instantiation, environment, and scoreboard (response checker), and achieved a complete checker, 90% coverage, and regression result of passing 1009 random testcase runs.

Researched the hardware design language Chisel, debugged Verilog module vin_cnt, developed Python program for memory mapping.

Implemented encryption algorithms in C and into RISC-V assembly code, optimized the script for Verilog module instantiation and signal definition.

Bachelor Of Applied Science - Basc, Computer Engineering

Bachelor Of Applied Science - Basc, Computer Engineering