ICT architecture and RTL design on DDR subsystem

RTL Design on system cache, focusing on encryption, authentication and memory tagging architecture.Synthesis timing analysis and design PPA optimization.

RTL design on system data cache with multiple configurations, i.e. cache capacity, associativity etc.Custom implementation on synthesis and netlist creation.Develop perl scripts for design release flow.

Designed circuits of different structures on low-voltage op-amp applied in delta-sigma integrator in Cadence.Simulated circuits and analyzed tradeoff between power, noise sensitivity and reliability.Compared performance under different component libraries and working environment.Assisted layout drawing and optimization of circuit modules.

Organized weekly lab and office hour, explained programming assignments.Reviewed course content, including pointer, array and sorting.Frequently discussed with professor and students on programming strategy.