Research and development of SoC and ASIC in the domains of Artificial Intelligence / Neural Networks

Hardware design for Intel processors.

Embedded software designer

EU hArtes project (Holistic Approach to Reconfigurable Real Time Embedded Systems) Designing online task scheduling and placement algorithms for FPGA-based partially reconfigurable systems. The algorithms monitor the utilization of the FPGA as well as dynamically assigning the configurable resource to arriving HW function kernels. The aim is to achieve better system performances by implementing reasonable SW/HW cooperation. Designing and implementing the APU version of “Molen” reconfigurable processor on Xilinx V4 FPGA (using VHDL). In this design, the PowerPC uses customer defined instructions to control the hardware kernels implemented on the FPGA. This design is the hardware platform which supports SW/HW cooperation. In addition, FPGA partial reconfiguration and Linux operating system are supported in the design. Designing and implementing the hardware interrupt mechanism for “Molen” reconfigurable processor. In this way, the real-time operating condition is supported. Designing and implementing the mechanism of memory parallelized access. In this work, we implemented a microcode-controlled arbitration logic on the FPGA to enable multiple hardware kernels to work in parallel as well as accessing the same memory.