Lecturer (part time) in Department of Computing for School of Engineering, Computing, and Built Environment at University of Wollongong, Malaysia (KDU Penang University College).My Specializations:Artificial Intelligence & Image ProcessingSystem Fundamentals & Operating SystemComputer NetworksICT, IT & Web TechnologiesVLSI & Physical Design (Semiconductor)Microprocessors and Digital Signal Processing (DSP)Teaching Subject(s) (under UOWM Computer Science Degree Programme):- Image Processing (Year 3)- System Fundamentals / Advanced Operating Systems (Year 2)Teaching Subject(s) (under USM Computer Science Degree - Offshore Programme)- Fundamentals of Logics and Artificial Intelligence (Year 1)

Private 1-to-1 Tuition for IGCSE/A-Level subjects- IGCSE Computer Science- IGCSE ICT (Information & Communication Technology)- IGCSE Mathematics- IGCSE Additional Mathematics- A-Level Computer Science- A-Level IT (Information Technology)- A-Level MathematicsProven Track Records:I have helped many IGCSE students who were failing initially before they came to me. And with my guidance and specialized teaching approach for less than 6 months, some has improved their grades to A and A*.

Digital MarketingWeb Development ServicesMobile App & Software DevelopmentIoT & Artificial Intelligence Automation with ESP8266 Micro-controllersMORE DETAILS AT: https://tagmetech.github.io/

Freelancer.com Profile: https://www.freelancer.com/u/lyehengfooWebsite Design using advanced Content Management System (CMS) (WordPress, Joomla)Web Development Frontend (HTML5, CSS, JavaScript, jQuery, BootStrap, W3CSS)Web Development Backend (PHP, Python, Ruby/Jekyll)Search Engine Optimization (SEO), Analytics and Website Optimisation.Professional Graphics Design & Video Editing

Job responsibilities & key accomplishments:Technical Lead for Physical Design Enginneering - Back-End custom ASIC chip design lead (both Block level and Full-chip level) for the United States of America, Japan and China clientsPhysical Design Engineeering - ASIC design from Gate-level Netlist to Physical Design and Timing signoff for Design Tapeout with EDA Tools from Synopsys, Cadence and Mentor Graphics.Design Automation Tools Development - Enhanced the existing design planning flow (covering die size estimation and cost estimation), floor-planning, power planning and power estimation for a more accurate early-design planning and quotation purposes.Design Automation Support - Developed and enhanced the ASIC design flow for front-end and back-end design methodology.Early Technology Process Node Adopter - Pioneered and worked through various design issues for the early process node adoption (includes new cutting edge double patterning 16nm FinFET). Enhanced new design flow and methodology for back-end physical design for this new process node.

Previously Altera (it is known as Intel PSG now)Job responsibilities & key accomplishments:Technical Lead for Design Automation - supporting both front-end and back-end IC Design engineers.Design Automation through scripts/programs (Cadence SKILL, PERL, shell scripting, C++, Python, Tcl).Design Methodology Development - circuit simulation and verification methodology, power planning and power modeling methodology.EDA Design Tools evaluation and qualification.Supported several EDA design tools - Cadence Virtuoso, Synopsys PrimeTime, Synopsys IC Compiler, Synopsys HSpice and HSIM for design simulation, Synopsys VCS for design verification, DRC and LVS verification tools (i.e. Synopsys IC Validator and Mentor Graphics Calibre), Apache Redhawk and Cadence LEC (formal verification tool)Pioneered IP library management and infrastructure development (project release handshake mechanism based on Synchronicity DesignSync).HardCopy/ASIC backend tools and flows development from scratch.Cadence SKILL based P-CELL for custom layout drawing - In-house pioneer developer from scratch.Cadence IC6.1 OpenAccess migration - project technical lead.Project Management roles supporting Design Automation projects.

Previously Altera (it is known as Intel PSG now)Job responsibilities:ASIC Physical Design (Custom Layout) layout drawingLayout Floor-planning - Block level and Full-chip levelDRC, LVS and EM verification for the chip designLayout Design Methodology development and continuous improvement

Job responsibilities:Technical support for photo-lithography process.Yield improvement for photo-lithography process to achieve 5-Sigma quality.Supervision for technicians and factory operators.