Muhammad Umair Bin S. Email & Phone Number

Karachi

-Conduct Signal Integrity simulations on High-speed structures.-Designing impedance-controlled Stack-up and transmission lines.-Interfacing high-speed impedance controlled connectors.-Schematic and Layout design.

Karāchi, Sindh, Pakistan

- Schematic Design (orCAD Capture CIS); Expertise in creating libraries (gated/non-gated components) and multipage design files using active, passive, and discrete components. Posses high knowledge in the usage of power ports and hierarchy connections.- Layout Design (Allegro PCB editor); Hands-on experience designing multi-layer PCB boards (more than 30 layers).- libraries(DRA) creation of components for layout; Expertise in creating complex multi-pin CPU/GPU libraries.- Component Placement (CPU/GPU, loopback structures, Decoupling capacitors, filtering Inductors, limiting resistors, and other circuitries) in the BRD file.- Assigning constraints. Expertise in defining physical, electrical and regional constraints of nets; differential pair spacing and coupling, single-ended spacing, via/drill keep out zones, neck down and variable coupling zones.- Signal routing; Strip line, Microstrip line, Dual strip line. (Expertise in Impedance Controlled, high speed, SE, Diff_pairs, mitered/un-mitered, non-impedance controlled. hands-on experience routing densely populated layers with copper pour and length/s-phase matching requirements).- Power planes; Hands-on experience sketching complex multilayer power planes on staggered and fine pitches.- Experience and hands-on experience in component selection(specifically Manufacturer and Manufacturer P/N) and extracting Cadence net-length, netlist, FAB files, etc and modifying them in cosmetically.- Gerber and Artwork creation; Expert in creating Gerber's, ODB++ and assembly files. Expertise in checking Gerber out files on CAM350 for open, short and missed nets.- Hands-on experience on PCB with dimensions as large as 22x16 inches (specifically Advantest 93K SoC)- Adequate knowledge of Stak-up layer structure and impedance controlled build-up.

Karāchi, Sindh, Pakistan

- Schematic Design (orCAD Capture); Expertise in creating libraries (DIE and BGA) multipage design files using active, passive, and discrete components. High knowledge of power ports and hierarchy connections.- Layout Design (Allegro Package Designer); Hands-on experience in designing multi-layer organic (MLO) for FLIP CHIP technology designs for Multi-Chip Module (.MCM) files. Expert in pitch transformation for DIE onto the suggested BGA/LGA using stitch/blind-buried vias (from C4 bumps to LGA/BGA).- libraries (DRA) creation of components for layout; Expertise in creating complex multi-pin DIE and CPU/GPU libraries.- Expertise in DIE-IN technique and ability to edit/add parts using parts manager without Schematic.- Assigning constraints. Expertise in defining physical, electrical, and regional constraints of nets; differential pair spacing and coupling, single-ended spacing, via/drill keep-out zones, neck down and variable coupling zones.- Blind buried via, controlled depth via stitching; Hands-on experience in pitch transformation using crankshaft via stitching technique for the pitch transformation- Signal routing; Strip line, Microstrip line, Dual strip line. Expertise in routing in copper pour layers to minimize crosstalk, well-versed in routing in tight DIE areas and sketching fanouts. Expert in routing diff pairs, single-ended, impedance controlled/un-controlled areas. Well-versed in matching length and s-phase of nets.- Power planes; Expert in sketching planes on outer and inner MLO layers alongside GND net and well versed in sketching complex fine-pitch PCB core layers.- Experience and hands-on experience in component selection (specifically Manufacturer and Manufacturer P/N) and extracting Cadence net-length, netlist, FAB files, etc and modifying them in cosmetically.- Gerber and Artwork creation; Expert in creating Gerber's, ODB++ and assembly files. Expertise in checking Gerber out files on CAM350 for open, short and missed nets.

Karachi. Pakistan

Master Of Engineering - Meng, Industrial Electronics

Thesis on placement of discrete components using Genetic Algorithm.

Bachelors Of Engineering, Electronics

Activities and Societies: 1. NEDUET 2016 Green Society: Dye-sensitized solar cell using beetroot. 2. SPEC 2017: Made LFR using IR sensors..