Collaboration, architecture, micro-architecture, verilog, spyglass, debug, dve, some verification, schematic capture, LEC, some PNR, Primetime, ICC for DRC/LVS/ERC/ECO. Documentation in HTML, PERL, TCL and dot(GraphViz).Responsible for design, architecture, micro-architecture, documentation and implementation of processor array blocks; table lookup unit, table memory management, cache, tags, hashing uint32/32 divider; cluster command and response interconnect, local power savings clk divider.Utilized Verilog, verilog assertions, Opus schematic capture, structured custom placement, Primetime for GHz timing closure, clock and scan insertion, ICC, LVS, DRC, LEC, and Tetramax to complete block design. Developed crucial DEF preroute perl script (DPW) used by all processor array blocks for clock and shield insertion and hardened power grid; earlier chips for prerouting busses alleviating routing congestion. Used ICC to hand fix LVS, DRC and ERC errors in several blocks; used for ECO. Wrote c-model for table memory management; used by software for usability testing. Developed an automatic top level buffer insertion flow and scripts to finish Antares PA. Collaborated with product engineer, board designers and software to root cause silicon issues; incorrect design IO test structure, DV pattern issues, async timing problem with TCAM interface.Evaluated, documented, scripted, deployed, integrated into full chip build, regressed and supported Atrenta/Spyglass verilog linter.Chips:LSQ, 16nm targeted for ASR9KProcyon, 22nm, taped-out 2016, for use in NCS1KAntares, 22nm, 2014, for use in NCS6KPita, 40nm, 2011, nPower/CRSYoda, 40nm, 2010, Quantum Flow / QFP ASR1KPopeye, 90nm, 2006, Quantum Flow /QFP ASR1KNT3CR, 130nm, 2003, PXF 7600 and CAT10K

Founding member Navarro Networks. Manager small design team responsible for RTL setup, debug, and implementing several blocks of the NT3 network processor chip currently used by Cisco Systems in their PXF line of 7600 and Cat10K systems.

Microprocessor architecture, behavioral modeling, schematic entry, timing closure, and silicon debug.Chips, M6/486sx, M1/M1RX 686, M2, MXi, Gobi.

Verilog and schematic work on 68332, 88110, and 88120