As a MD (Mask Designer) at Xeon Performance Group • Review and closure of partition PV signoff • Worked on multiple SoC projects at partition and SoC Level • Worked on Placement, PG and Signal Track planning, ECO Routing, DRCs, LVS, Density, RV • Worked on SoC Top layer Critical Antenna fixes of one of the biggest Graphical Server Processor. • Worked on SOC and Full Chip level Till Tape-in. Proficiency in Automation in TCL for IC Compiler • Worked on IC compiler to develop many GUI based… Show more As a MD (Mask Designer) at Xeon Performance Group • Review and closure of partition PV signoff • Worked on multiple SoC projects at partition and SoC Level • Worked on Placement, PG and Signal Track planning, ECO Routing, DRCs, LVS, Density, RV • Worked on SoC Top layer Critical Antenna fixes of one of the biggest Graphical Server Processor. • Worked on SOC and Full Chip level Till Tape-in. Proficiency in Automation in TCL for IC Compiler • Worked on IC compiler to develop many GUI based utilities (in TCL/TK) which helped whole team to accelerate their work speed and made DRC cleaning easier. • Also worked on older ICC2 Utilities used in earlier process to make them compatible with next Technologies nodes also made some of them technology independent. • Developed Hotkey based macro scripts to improve quality and efficiency. Some of Scripts are ▪ Error Highlighter ▪ VT layer Error fixer ▪ Via Density fixer ▪ Short Remover ▪ Pattern Porter ▪ Area Computer ▪ Shapes merger ▪ Auto-router ▪ Proper Version of diode Cell finder Show less