. Experienced Design Verification engineer with Bachelors degree in Electronics & Communication Engineering & PostGraduate Diploma in Telecommunications .. Experience in Design verification with HDL and HVLs • Strong skills on System Verilog, UVM methodology, Assertion based verification , C.• Development of verification environment in UVM methodology from scratch.• Expertise in developing coverage driven constraint random verification.• Domain expertise include I2C, AHB,SPI,AXI , PCIe ,UART, NOC,bridges .• Developing testplans, Mapping to functional coverage, analyzing and closing code and functional coverage.• Develop ,integrate the reference C system models in SV/UVM environment.• Integrate third party VIP in SV/UVM verification environment. • Good experience with ARM and C-based system-level verification environment. • Experience in DV automation and regression management with scripts Perl, Python , Shell,Linux .