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Michael Erdmann Email & Phone Number
Senior Physical Design Engineer (DFT): Micron Technology
at
ForwardEdge ASIC
1 work email found
@micron.com
LinkedIn matched
4 data sources
Profile completeness 86%
Current company
Role
Senior Physical Design Engineer (DFT): Micron Technology
Location
St Paul, Minnesota, United States
Company size
Who is Michael Erdmann? Overview
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Quick answer
Michael Erdmann is listed as Senior Physical Design Engineer (DFT): Micron Technology at ForwardEdge ASIC, a company with 77 employees, based in St Paul, Minnesota, United States. AeroLeads shows a work email signal at micron.com and a matched LinkedIn profile for Michael Erdmann.
Michael Erdmann previously worked as Senior Physical Design Engineer at Micron Technology and Senior Physical Design Engineer at Micron Technology. Michael Erdmann holds Bachelor'S Degree, Electrical Engineering from University Of Minnesota.
Company email context
Email format at ForwardEdge ASIC
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{first_initial}{last}@micron.com
86% confidence
AeroLeads found 1 current-domain work email signal for Michael Erdmann. Compare company email patterns before reaching out.
Profile bio
About Michael Erdmann
An experienced engineer seeking to advance my career while expanding my knowledge in the field of High-Performance ASICs. A dependable, self-driven, and highly-verstile innovator who is often called-upon to identify root cause and develop solutions in areas requiring expedited resolution. A fierce advocate for all Team-focused processes that minimize inefficiencies while leveraging existing expertises, such as: Continuous Integration, Process Automation, and Lifetime Learning.When not at work, I enjoy spending time with my children or with friends. My personal time is often spent mountain-biking, skiing, and golfing. Life is short, so I proactively seek-out new experiences and adventures.
Current workplace
Michael Erdmann's current company
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Forwardedge Asic
7 roles
Michael Erdmann work experience
A career timeline built from the work history available for this profile.
Senior Physical Design Engineer
Senior Physical Design Engineer
Current- Using industry-standard Siemens toolset, generate Scan and Boundary Scan solutions, and perform ATPG for all Tester programs (and Advanced Compute programs, as needed). Produce STIL patterns for manufacturing ATE..
- Enhanced existing Scan scripting for reuse on multiple projects, extract key DFT metrics into readable reports for progress monitoring and comparative analysis. Created automation for generation of patterns, and.
Jun 2018 - Present
Asic Engineer
- Designed, built, and supported lab test-stations (rack and single-seat). Co-managed Linux distributions for python-based validation environment for NVDIMM product.
- Performed system-level integration of NVDIMM product into High Performance servers for multiple existing & emerging Tier1 customers. Worked directly with driver and BIOS teams to resolve several blocking issues.
- Developed proposal for a state-agnostic sequence to force uncompliant systems into required (self-refresh) state in preparation for power-loss events. Worked with Firmware team to successfully implement & validate.
- Using low-cost analyzer, co-authored script to parse & map captured SMBus (BIOS) traffic onto part-specific documentation. This rapidly-expedited the resolution of multiple existing (and undiscovered) bugs during.
Jun 2015 - Jun 2018
Design Verification Engineer
- Developed UVM agents to verify 3rd-party VendorIP (DDR-based memory controller).
- Created CoverGroups, Assertions, Constrained Randoms that fulfilled all achievable Functional and Coverage line items in verification plan.
- Updated existing simulation flows to produce pareto charts for Nightly/Weekly regressions.
Jun 2012 - Jun 2015
Asic Design Engineer
- Designer of ATA/SerialATA module for Micron’s 1st PCIE-based SSD. Adapted design for integration with AHCI controller. Further refined design to provide front-line triage of lab-failures for all internal customers, and.
- Provided on-site FAE support for Engineering Sample deployed to Tier1 customer. Identified root-cause using above telemetry and made several key design updates to mature product support, including new generic servicing.
- Created internal Aggregate Tag Retirement and parallel pipelining scheme that complied with industry-standards, and outperformed competitors (Patent awarded).
- Performed numerous exploratory characterizations of DDR/DDR2 to maximize performance while minimizing latencies.
Jun 2000 - Jun 2012
Product Engineering Intern
Conducted Design-of-Experiment (DOEs) to reduce Tribology defects, process-related Slider defects, and HGAs/HSAs defects by characterizing Recording Head transducer performance and refining GMR head designs in rotating media HDD programs.
Sep 1996 - May 2000
2 education records
Michael Erdmann education
Bachelor'S Degree, Electrical Engineering
University Of Minnesota
Undergraduate, Pre-Engineering
University Of Minnesota Morris
FAQ
Frequently asked questions about Michael Erdmann
Quick answers generated from the profile data available on this page.
What company does Michael Erdmann work for?
Michael Erdmann works for ForwardEdge ASIC.
What is Michael Erdmann's role at ForwardEdge ASIC?
Michael Erdmann is listed as Senior Physical Design Engineer (DFT): Micron Technology at ForwardEdge ASIC.
What is Michael Erdmann's email address?
AeroLeads has found 1 work email signal at @micron.com for Michael Erdmann at ForwardEdge ASIC.
Where is Michael Erdmann based?
Michael Erdmann is based in St Paul, Minnesota, United States while working with ForwardEdge ASIC.
What companies has Michael Erdmann worked for?
Michael Erdmann has worked for Forwardedge Asic, Micron Technology, and Seagate Technology.
How can I contact Michael Erdmann?
You can use AeroLeads to view verified contact signals for Michael Erdmann at ForwardEdge ASIC, including work email, phone, and LinkedIn data when available.
What schools did Michael Erdmann attend?
Michael Erdmann holds Bachelor'S Degree, Electrical Engineering from University Of Minnesota.
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