Gana
CurrentMachine Learning Compilers, AI acceleration, Quantization, Graph Partitioning & Scheduling, Optimizations & RetargetabilityConstraint driven PHV Allocation; Clustering, VLIW aligned Slices for SDN protocol independent Match Action pipelinesKernel programming, NFS, LFS, Deadlock detection & synchronization, device drivers, Storage Operating SystemsHardware Verification: Mixed language Verilog/VHDL, Mixed paradigm event-driven/cycle-based/hybrid, Hardware Synthesis: silicon compilation, Control-Flow to Data-Flow transformations, FPGA-based reconfigurable architectures: cryptographyArchitect/Author of compilers: Pascal, Ada, C, C++, Java, VHDL, Verilog, XML, Parallel Computing, OpenMP Procedure Outlining for parallel runtimes, autoprivatization, Procedure Inlining, reduce Cyclomatic Complexity of programs, Software Transactional Memory, Vectorization,Thread Analysis, Race Detection, Model Checking, Functional Languages for many-core architectures, Static & Dynamic Analyses software tools, ModularityMicroprocessor definition, ISA logic, memory subsystem w/ ECC, bus architectureFinancial Servers: WorkFlow, CBRS, Back office ACATEOD,MF Activity, Tuxedo transactions, Oracle, Sybase, DBGen SQLD, PL/SQL3D mapping human anatomy to C++ objects, data representation & simulationConstruction Compiler amalgam of XML/XSD compilation to C++, Java, REST APIs, Node.js, Python, MongoDB, Hadoop, SQL, NoSQL, Apache web servers, Energy Models & Management, Constraint Solvers, Data AnalyticsSimulator including Process Levelization, US Patent 5784593, 1998.Method & apparatus using a Memory model, US Patent 6053948, 1998.Deadlock Detection framework combining Static & Dynamic Analyses, 2008Reader-Writer Locks algorithm & implementation, 2008“Happens-Before” analysis, pruning false positives, 2008Cloud Medical Record Access Apparatus & Method of Operation, Provisional Patent, Attorney Docket K-PTNTR201404P, 2014
