Mahender Kumar Email & Phone Number

Santa Clara California

Foundry interface technologist for 7nm and 5nm CMOS technology nodes for AveraSemi ASIC product design teams. Managed and delivered closure of device, technology, reliability, and PDK issues on a very tight schedule to meet ASIC hardware product design performance, power, yield, and reliability requirements. Created a special wafer acceptance test (WAT) critical parameters list (CPL) document beyond provided by the foundry for ASIC product development cycle time improvement. Also, I provided the technology education training to ASIC design teams to speed up the product design cycle time.

Santa Clara, California And Malta, New York

Leading-edge 7nm and 5nm semiconductor CMOS technology definition: process flow and device architectures, process specifications for fab and PEX /device models, design rules, standard cells and SRAM memory bit cell definition to meet hardware design performance, power, yield, and reliability requirements.Semiconductor process integration and device technology leader for Design Manual Review Board and design Waiver Review Board (WRB). Business process development for design Waiver Review Board (WRB) to improve work efficiency>30%.Played leadership role for corporate-level pilot program for patent IP infringement evaluation methodology development by teamwork with the legal team. It is expected to have >5M saving or earning in patent IP from the competition.Product design productivity focus area in-charge for SystemX (Stanford University): Bring in best practices for analog-mixed signal (AMS) as well as for digital logic design to solve customer silicon IP issues.

Malta, New York

Improved 20nm semiconductor CMOS technology for product development and manufacturing compliance of process specifications, design rule with product performance, power, yield, and lifecycle reliability requirements by working together with technology development and manufacturing organizations.

East Fishkill, New York

Played a senior technical leadership role in definition, development, and manufacturing of 65nm, 32nm and 22nm semiconductor silicon-on-insulator (SOI) CMOS technologies for IBM server system product as well as for ASIC product on a very aggressive schedule.Semiconductor process technology representative to work with IBM server and ASIC product design teams to resolve technical issues to improve product performance, power, density, yield, and reliability. It improved product delivery schedule and specifications expectations by >5%.Comprehensive design of experiments (DOE) for process yield and reliability learning test structures definition for by cross organization collaboration with technology development and manufacturing teams. It improved yield and schedule by >15%.Champion responsible for process specifications and design rule validations to ensure product manufacturing meets the performance, power, density, yield, and reliability specification to exceed product quality requirement.Technical manager for technology resources: hardware lot allocations, hardware lots priority, failure analysis resources etc. Improved the utilization of resources by>30%.

East Fishkill, New York

Demonstrated the feasibility of semiconductor SOI embedded DRAM (eDRAM) in 90nm SOI CMOS process technology. Which has been used in IBM server product starting from semiconductor SOI CMOS 45nm technology node. This innovation and vision has high impact on system performance for IBM SOI CMOS technology and server hardware product.Semiconductor process integration flow definition and feasibility demonstration of SOI SiGe vertical bipolar junction transistor (V-BJT) which is compatible with high-performance SOI CMOS technology for RF systems hardware engineering. Champion responsible for verification of benefit of IBM semiconductor SOI CMOS 90nm technology for AMD microprocessor hardware engineering product in IBM semiconductor research and development fabrication facility using AMD mask set. It earned IBM >50M.

New Delhi, India

Demonstrated integrated photonics optical splinter/divider feasibility and worked on MEMS cantilevers.

Ahmedabad,Gujrat, India

Collected data for a remote-sensing satellite camera calibration. Calibration of camera improved the data quality, this satellite data created market opportunities for ISRO India to sell to other countries. It created international market for ISRO >10M.

Doctor Of Philosophy (Ph.D.), Electrical And Electronics Engineering

Activities and Societies: University cricket team.Focus on device and technology.

Master'S Degree, Electronics

Activities and Societies: Cultural activities.Device and technology.

Bachelor'S Degree, Electronics

Activities and Societies: Social services.