Senior Engineer
CurrentProject 1Worked on 16 nm FF+ technology and resonsible for PnR, physical verification, power IR/EM analysis, flow development using TCL, Perl.Project 2Worked on 40nm technology and responsible for pnr, timing closure and power analysis. Project 3Worked on technical experiment on 7 nm FF+ to check impact of different metal layers and length driven by cells on cross-talk. Also worked on HSpice simulation to check delay and transition values. (published technical paper on this). Handled two blocks from netlist to signoff. Also worked on custom block (including sub-blocks) for PnR, timing and congestion optimization, flow development. Developed custom cells like synchronizer.Project 4Was responsible for physical verification at chip level and block level.Project 5Responsible for handling two blocks from netlist to signoff. Have experience on multimillion instance design and higher memories. Worked on serdes IP block where performed custom cell placement and routing for refclk, power planning for analog IPs. Performed multibit flops experiment to check timing, congestion and power impact on design. Was responsible for analyzing flow issues and providing solutions.Project 6Working on two blocks having high instance count and high number of memories, timing and congestion critical design. also working on hierarchical design.ToolsPNR tool: ICC, InnovusSTA tool: PT, TempusPower tool: Redhawk, VoltusPhysical verification: IC validatorExtraction tool: starRCHSpice
