Mallika Prakash Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

Bangalore Urban, Karnataka, India

- Art curation and related services for residential & corporate interiors.- Working closely with architects & interior designers to curate art for their interior projects.- Managing client acquisition & onboarding.- Liaison between clients and artists. - Driving social media strategy and visual design.- Driving development of a faster e-commerce-driven website.- Managing cataloguing of the artworks to ensure true representation on online channels. - Planning & execution for exhibitions and art/design fairs

Illustration & Design - Design Proposals, Look books, Merchandise Design, Story Book illustrator, Logo Design - Merchandise Designer - Digital illustrations for T-shirts for Triumph India, Classic Legends, Bikenbiker, Candida Louis and Moto Art Show. - Book Design and Illustrations - A Covid-19 Story - Laid out and designed a short novel targeted towards young adults to educate them about the COVID-19 vaccines. - Edited the story and created digital illustrations for the book - Logo Designer Content Creation - Photography : product, lifestyle - Videography : lifestyle, introductions, interviews - Post processing : Colour correction, editingWall Muralist - Painted walls for Bikenbiker and private clientsEvent setup - Artist curation, fundraising, marketing & PR gallery setup, sales and accountsCommissioned paintings for private collectors.

San Francisco / Bangalore

Moto Art Show is India's first exclusive gallery art show dedicated to motorcycle art.

Standard cell library design in Finfet and CMOS technologies .Expert in area/power/performance/noise cell/macro characterization, cell extraction, related physical flows and library database management including compilation and release, data comparison and analysis.Trained, mentored and managed new hires and junior engineers.Experienced in tapeout ready custom clock pregrid design.Experienced in datapath physical design.

- Full custom block level layout using Cadence Virtuoso and Nanoroute in 65nm. - Leaf cell layout done using CCAR and responsible for fixing charge-sharing problems in dynamic circuit layouts.- Layout verification done using Assura DRC and LVC.

* Developed and supported IP libraries for the Silistix standard cell based globally-asynchronous locally -synchronous (GALS) Network-on-Chip solution. * Developed physical design methodologies for synthesis, area and timing driven place and route, clock tree synthesis, clock gating, scan insertion to enable simulation based power analysis using Magma’s Blast suite of tools. * Developed separate kgates area and mm2 area estimation models for the IP libraries. The network components were characterized in 90nm and 65nm processes using Design Compiler and BlastFusion respectively. * Developed separate leakage, idle and dynamic power models for the IP libraries in 90nm using BlastFusion’s power analysis tool and Modelsim. * All flows were automated using Tcl and/or Perl.

Developed a push-button automated flow for library characterization and static timing analysis of asynchronous circuits that are not supported by commercial tools to enable back-annotated power and timing simulations and static timing and performance verification as part of a Master’s thesis. * Developed a methodology to characterize timing and power information into a Liberty file for a library of dual-rail domino pre-charged circuits from Spice simulations in 180nm. * Did custom layouts of the above library of cells in 180nm and took them through DRC, LVS and extraction to yield LEF and spice netlists using Cadence tools. * Developed a validation flow using Cadence SoC Encounter and NCVerilog to compare the quality of the Liberty file against Spice. * Developed static timing analysis and performance verification methodologies for dual-rail pre-charged single and multi-level domino circuits with timing loops and complicated timing constraints using PrimeTime. * Automation was done by using Tcl and/or PerlPatent Pending: 20090210841 Static Timing Analysis of Template-based Asynchronous Circuits

* Developed a methodology to do static timing analysis using PrimeTime for standard cell-based asynchronous circuits that have timing loops and relative timing constraints as part of a Master’s thesis. * Automation done using Tcl.

* Designed a generic standard cell library and interface for a VLSI System on Chip design utilizing Cadence tools and worked on the technical documentation. * Designed I/O pads for a 90nm process. Generated the layouts automatically using SKILL.

M.S, Computer Engineering

Thesis Title: "Library Characterization and Static Timing Analysis of Template Based Asynchronous Circuits"

B.S, Computer Engineering

Activities and Societies: Vice President. IEEE Student Chapter at IIT. August 2002 – May 2003

Bachelor'S Degree, Computer Engineering