Mark A. Email & Phone Number

I manage Mil-Aero and regional technical/engagements for clients across the West Coast region for the Calibre IC layout verification tools, supporting over 50 clients. I also manage the W/W activities for rolling out a new tool for reliability analysis to the field teams.- Responsible for creating relationships with CTO's and technical managers to promote.

Glendale, California, US

• Development of new business applications for NASA/JPL developed Artificial Intelligence. I lead the technical client engagement process, understanding their needs and qualifying opportunities to automate their.
• Researched new markets, identified leads, responded to RFI/RFP’s and developed the go to market & engagement strategy to approach clients in Aerospace, Auto, Fintech, Energy on how AI can enhance their business.
• Managed SEs, provided technical selling skill training and developed an internal knowledge base for the team to access use cases, solution designs, POCs, project scopes.
• Ran deep dive discovery sessions with clients and technical teams to achieve technical alignment and develop a POC project plan, examples include Oil & Gas - well management, refinery planning, Auto – distracted.

Burlington, MA, US

• I manage sales engineering with clients in their DevOps environment, successfully helping them make better use of Open Source Software in their products by helping them manage content, security and licensing. Won new.
• Expert in helping clients automate their management of OSS license compliance and security vulnerabilities in their development and build tools DevOps environment to safely increase its use.
• Strategize and plan the engagement and POC process to enable clients to quickly see the value of running automated compliance and security tools during builds to proactively manage OSS components.
• Work with internal product teams to co-build new solutions that successfully work in clients IDE/CICD production environments.

San Jose, California, US

• Responsible for business development in North America for new electronic design automation software products. Worked with regional sales teams to actively pursue accounts and negotiated solutions with new customers.
• Closed new business for the North American region for major technology companies, managing a pipeline of over 20 customers.
• Drove product positioning, negotiated technical enhancements. Coordinated with product managers and development teams on content and release schedules.
• Successfully managed product trials, demonstrating the technology and ROI. Performed on-site product bring-up and initial configuration for customers to ‘get-going’ with the products.
• Authored marketing plans, using online and sales channels to reach target audiences and generate new business opportunities. Evangelized product value with presentations and demos at conferences and trade shows.

Wilsonville, OR, US

• Customer facing technical marketing role driving adoption of new ASIC silicon chip verification products, working with engineering, field AE’s and customers defining and running ASIC layout verification (parasitic.
• Managed strategic product evaluations in ASIC, analog and memory applications, established customer relationships, capturing requirements and liaising with engineering to deliver new product features.
• Technical product expert in parasitic extraction and layout verification for Analog/RF and Digital design flows, foundry process characterization at 90/65/45nm nodes including TSMC/IBM in-die variation modeling.

Wilsonville, OR, US

• I coordinated pre-sales and product marketing activities across Europe for Calibre IC layout verification software products for silicon chip modeling. I worked with engineering and product teams to define key.
• Managed key customer engagements and technical evaluations, driving closure with ‘top 10’ customers.
• Expert knowledge on layout extraction and verification in analog and digital flows, running customer tool evaluations and providing on-site consultancy.

US

• Field Applications Engineer role driving adoption of new DFT Logic and Memory BIST products. Managed customer evaluations of BIST products and verification with simulation.
• Prospected and engaged with clients to evaluate using Logic Visions embedded pseudo-random at-speed HDL test functionality into their RTL designs.
• Expert in on-chip ATPG and simulation/detection along with traditional DFT scan-chain test methods.

San Jose, California, US

Senior applications engineering and consulting role for EDA physical design software products. Successfully managed large ASIC design tape-outs for internet, aerospace, military customers across the EU and Middle East, successfully taped-out multiple 180/90nm designs.

Managed silicon chip physical design tape-outs for Mil/Aero customers on sea of gates architectures. Delivered over 20 chips for military, space and commercial customers. I was in charge of working with clients to complete placement, routing and manual cell/route editing, DFT/ATPG, clock tree synthesis, post-layout back-annotation/simulation timing.

Ceng Chartered Engineer

Msc Degree, Computer Aided Engineering

Beng Degree, Electronic Engineering

National Diploma, Electronic Engineering