Devised and implemented Design for Manufacturing (DFM) methodologies for rapidly processing a full chip layout and diagnosing problem spots. This included correlating similar patterns, outlier detection, and feedback flows for troubleshooting existing problems or fixing issues before they occur.

Implemented fast physical electromagnetic model for accurate simulation and optimization of diffractive optic element (DOE) lenses. Utilized methods akin to thick mask modeling of photomasks applied to DOE technology.

Developed software in Java for rigorous and large scale lithography simulators. Interacted directly with customers on implementing new features. Worked on both new simulator infrastructure and GUI implementation.

Defined lithography process techniques for 7nm and 5nm nodes via early modeling, source definition, test mask design and simulation for enabling EUV technology in manufacturing. Developed platform for automated large scale simulation for enhancing modeling capabilities via optimization.

Worked on the 22nm, 14nm, 10nm, 7nm technology nodes. Developed novel methods for modeling wafer data, resolution enhancement techniques and source mask optimization. Implemented optical proximity correction (OPC) algorithms for large scale enablement. Devised metrology algorithms for improved modeling.