Manas Karanjekar Email & Phone Number

Currently working as a Software Engineer with focus on Formal Verification techniques.I completed my Masters in Electrical and Computer Engineering from Portland State University, specializing in Computer Architecture and Design Verification. I love coding and experimenting on small computer architecture units such as caches, pipeline and branch prediction simulators. I am also learning various verification methodologies such as formal verification, functional verification and emulation to help recognize flaws in digital designs. Apart from academics, I am a public speaking enthusiast and regular participant in events where I can engage and interact with people from diverse backgrounds.Core competencies:✯ HDLs : Verilog, SystemVerilog✯ Programming Languages : C, Java✯ Scripting Languages : Perl, Python✯ Verification Methodologies : Functional Verification,UVM,Assertion Based Verification✯ Verification/Logic Design Tools : Cadence JasperGold, Xilinx ISE, ModelSIM, QuestaVerify✯ Operating Systems : Unix,Windows

Listed skills include Public Speaking, Debate, Xilinx Ise, Keil, and 20 others.