Pre-Silicon Validation Engineer
CurrentMember of team responsible for development and verification of a high performance networking and communication architecture, also known as Omni-path fabric.
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@intel.com
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Maneet B. is listed as Pre-Silicon Validation Engineer at Intel Corporation, a with 10 employees, based in Greater Boston, United States. AeroLeads shows a work email signal at intel.com and a matched LinkedIn profile for Maneet B..
Maneet B. previously worked as Verification Design Engineer at Lsi Corporation and Intern Hardware Architect/Graduate Technical Intern at Intel Corporation, Intel Mobile Communications (Imc). Maneet B. holds Master'S, Electrical Engineering from University Of Minnesota.
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• Masters degree in Electrical Engineering specializing in VLSI and computer architecture• Experienced with System Verilog based OVM verification environment development• Experienced with constrained random based verification, functional coverage and assertions • Hand-on work experience and domain knowledge of VLSI concepts, digital circuits and computer architecture
Listed skills include Verilog, Vhdl, Cadence Virtuoso, Systemverilog, and 23 others.
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Santa Clara, California, Us
Member of team responsible for development and verification of a high performance networking and communication architecture, also known as Omni-path fabric.
San Jose, Ca, Us
· Design and development of a System Verilog based OVM environment for a hard disk controller· Part of design team for verification of read channel servo sub block for various projects· Responsible for verification closure of block/system/chip level functions. Maintaining, tracking and closing design bugs.· Hand-on work experience with constrained random verification techniques and functional, code and toggle coverage · Work experience with Cadence Incisive and Synopsys VCS simulating environments· Work experience with Verdi 3 Automated Debug System and DVE Advanced Debugging and Visualization Environment
Santa Clara, California, Us
• Implemented power model of a baseband modem platform in an industry standard tool• Worked with power saving/clock gating techniques and power modelling strategies• Planned and implemented design of excel model after analysis of tool’s limitations, intrinsic power calculation and subsequently design strategies• Documented the comparison of new model with the existing design and presented results to system experts
Bangalore, Karnataka, In
• Responsible for the following : Design and testing of a 2G and a 3G/4G Base Transceiver Station (BTS) Design and development of an RF Multi-Carrier Power Amplifier (MCPA) sub-system Testing of RF designs using Network and spectrum Analyzers Simulation of digital pre-distortion algorithm on an FPGA using Verilog• Used Cadence schematic and layout tools • Rigorous training in FPGA and board system design
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Yun Yi Lim
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Moises Becerra Perez
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Mindy Cheng
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Tal Oved
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Kaiann Fu
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Joshua Fischer
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Noam Bar
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Ratnesh Kumbhkar
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Maneet B. works for Intel Corporation.
Maneet B. is listed as Pre-Silicon Validation Engineer at Intel Corporation.
AeroLeads has found 1 work email signal at @intel.com for Maneet B. at Intel Corporation.
Maneet B. is based in Greater Boston, United States while working with Intel Corporation.
Maneet B. has worked for Intel Corporation, Lsi Corporation, Intel Corporation, Intel Mobile Communications (Imc), and Wipro Technologies.
Maneet B.'s colleagues at Intel Corporation include Yuda Maulana, Yun Yi Lim, Bart Corsey, Moises Becerra Perez, and Mindy Cheng.
You can use AeroLeads to view verified contact signals for Maneet B. at Intel Corporation, including work email, phone, and LinkedIn data when available.
Maneet B. holds Master'S, Electrical Engineering from University Of Minnesota.
Maneet B. is listed with skills including Verilog, Vhdl, Cadence Virtuoso, Systemverilog, Algorithms, Modelsim, C++, and Xilinx Ise.
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